Power Optimization Methods of Energy Recovery Circuits

DAI Hong-yu; ZHANG Sheng; ZHOU Run-de

Chin. J. Semicond. > 2002, Volume 23 > Issue 9 > 996-1000

CONTENTS

Power Optimization Methods of Energy Recovery Circuits

DAI Hong-yu, ZHANG Sheng and ZHOU Run-de

+ Author Affiliations

Abstract:

The non adiabatic loss in energy recovery circuit is proportional to C_LΔV². Two methods are presented to lower the two factors of C_L and ΔV. High efficient energy recovery logic (HEERL) circuit utilizes bootstrap effect to decrease node residential voltage ΔV. Improved energy recovery logic (IERL) adds extra recovery path to improve the recovery efficiency. At the same time the control node has C_AΔV² non adiabatic loss, but the total circuit power is saved. Compared with other energy recovery circuits, the two circuits presented show more than 50% power saving with only small area loss.

Key words: energy recovery, low power, adiabatic computation, CMOS circuit

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