| Citation: |
Wang Jinhui, Gong Na, Feng Shoubo, Duan Liying, Hou Ligang, Wu Wuchen, Dong Limin. A Novel p-Type Domino AND Gate Design for Sub-65nm CMOS Technologies[J]. Journal of Semiconductors, 2007, 28(11): 1818-1823.
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Wang J H, Gong N, Feng S B, Duan L Y, Hou L G, Wu W C, Dong L M. A Novel p-Type Domino AND Gate Design for Sub-65nm CMOS Technologies[J]. Chin. J. Semicond., 2007, 28(11): 1818.
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A Novel p-Type Domino AND Gate Design for Sub-65nm CMOS Technologies
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Abstract
A novel p-type Domino AND gate utilizing the sleep transistor,dual threshold voltage,and source following evaluation gate (SEPG) techniques is proposed.HSPICE simulation results prove that the leakage current of the proposed design can be reduced by 43%,62%,and 67% while improving the noise margin 3.4%,23.6%,and 13.7% when compared to standard dual Vt Dominos,standard low Vt dominos,and the SEFG structure under similar delay time,respectively.Therefore,the proposed Dominos AND gate solves the high leakage current and deteriorated robustness problem in sub-65nm CMOS technologies.Finally,the inputs and clock signals combination sleep state dependent on leakage current characteristics is analyzed,and the optimal sleep state is obtained.-
Keywords:
- low power,
- leakage current,
- p-type Dominos AND gate,
- noise immunity
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References
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Proportional views
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