Abstract: This paper presents the design considerations and implementation of a novel topology digital multi-stage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthesis.In an effort to reduce the complexity and dissipation,a pipeline technique has been used, and the proposed carry save tree (CST) algorithm optimizes the multi-input adder structure.The circuit has been verified through Matlab simulation,ASIC implementation,and FPGA experiment,which exhibits high performance and potential for a gigahertz range,low-power monolithic CMOS frequency synthesizer.

Key words: ΔΣ modulator, fractional-N frequency synthesis, MASH architecture