| Citation: |
Guo Baozeng, Gong Na, Wang Jinhui. Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies[J]. Journal of Semiconductors, 2006, 27(5): 804-811.
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Guo B Z, Gong N, Wang J H. Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies[J]. Chin. J. Semicond., 2006, 27(5): 804.
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Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies
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Abstract
Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed.Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE.The simulation results show that the proposed circuits effectively lower the active power,reduce the total leakage current,and enhance speed under similar noise immunity conditions.The active power of the two proposed circuits can be reduced by up to 8.8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage.At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4%,respectively.Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.-
Keywords:
- low power,
- leakage current,
- OR dominos,
- noise immunity
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References
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Proportional views
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