1. Introduction

Millimeter-wave and terahertz-wave frequency wave sources are widely used for a variety of applications, such as molecular spectroscopy, atmospheric remote sensing, scaled radar range systems, sensing and monitoring of chemical and biological molecules, increased security for point-to-point communications as well as covert battlefield communications. The widespread utilization of millimeter-wave and terahertz-wave is very slow. The primarily reason for this is a lack of broad band, high power, high stability and compact sources. Existing millimeter and terahertz-wave sources can be realized in the following ways, oscillator sources, photonic mixing, and frequency multiplication. Although the sources mentioned above are very useful, they each have their own limitations. Some are inherently limited in output power or require cryogenic cooling, and others are limited by their size, cost, or complexity. At present, for generating high efficiency, high output power, and compact millimeter and terahertz-wave sources, frequency multiplication is still a very effective method^[1-13].

W-band hybrid integrated quartz based GaAs Schottky diode doublers are fabricated and tested. Full-wave analysis is applied for circuit optimization. All passive networks of the circuit, such as the low pass filter, the E-plane waveguide for stripping transitions, input and output matching networks, and passive diode parts are analyzed by using electromagnetic (EM) simulators. The exported $S$-parameters of the optimized complete circuit are used for harmonic balanced analysis (HBA) in ADS. The highest measured output power is 29.5 mW at 80 GHz with an input power of 275 mW, and power is higher than 15 mW in 76-94 GHz and above, and more than 10 mW in 70-96 GHz. The output power of the doubler is high enough for pumping commonly applied W-band fundamental or G-band subharmonic mixers without any amplifier, because W-band commercial power amplifiers are usually unavailable.

2. Circuit design

An iterative "divide and combine" design approach is adopted, breaking up the doubler circuit into different parts, where each part is simulated and optimized individually. The different parts are then combined and optimized together, and this process is repeated for the required efficiency. The design flow chart of the doubler is given in Fig. 1.

Figure  1.  Frequency doubler design flow chart.

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2.1 Diode embedding impedance calculation

In the doubler, a flip chip planar Schottky varactor chip with four diodes integrated in an antiseries configuration is adopted. The diode is mounted as shown in Fig. 2, input signals are out-of-phase to the diode chip, the generated even harmonic signals are in-phase at the output port, and the generated odd harmonic signals are out-of-phase and cannot propagate to the output port. Therefore, the multiply circuit can realize balanced even harmonic frequency multiplication, as described in Fig. 3^[1]. The non-linear Schottky junction is modeled by SPICE parameters, which are entered into the ideal diode model in ADS to simulate the diode characteristic. The SPICE parameters are extracted by the measured $I$-$V$ curve, and zero bias voltage junction capacitance can be calculated by anode area and epitaxial thickness. The diode SPICE parameters are $R_{\rm S}$ $=$ 4.5 $\Omega$, $n=$ 1.15, $C_{\rm j0}$ $=$ 0.052 pF, $I_{\rm S}$ $=$ 0.45 fA. To be able to accurately predict the optimum diode chip embedding impedances, adding the influence of the diode chip parasitic, a full 3D EM simulation of the diode chip in its circuit environment is analyzed to find the optimum embedding impedances. The 3D-EM simulation of the diode chip with a lumped port is applied at the Schottky diode junction; the diode non-linear part and passive circuit part are then combined together^[14]. The diode pad interface is extruded and the transmission line ports are later de-embedded back to the diode reference planes, as described in Fig. 2. It is an essential operation that enables precise modeling. In fact, if the ports are too close to discontinuities they can interfere with the near field around these discontinuities and therefore alter calculation results. The $S$-parameter file of the diode chip is exported for diode model embedding impedance discussion in ADS. The diode component is connected to the internal port and down to ground, by running HBA in ADS, the diode optimum input pump frequency and output second harmonic frequency impedance is calculated, and the diode impedances at pump frequency $Z_{\rm in}$($f_{\rm p})$ and the second harmonic frequency $Z_{\rm out}$($f_{\rm 2p})$ are found to be 18 -j86 and 34 -j46 respectively. The value of impedance will be used thereafter to synthesize the doubler circuit.

Figure  2.  Diode chip model in HFSS.

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Figure  3.  Balanced frequency doubler schematic.

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2.2 Circuit optimization

The doubler circuit structure is shown in Fig. 4, the pump frequency TE$_{10}$ mode is the only wave allowed to propagate in the input circuit, the effective input back short (L2) is tuned for the maximum transmission of the pump signals to the diode. The following quasi-coaxial waveguide channel is used to sufficiently cut off the propagation of the input frequency and act as an effective input frequency backshort. The length of the reduced-height waveguide (L1) and the location of the input back-short are optimized to achieve a small return loss to the input port signals. The output section consists of the waveguide-microstrip transition and the suspended microstrip quartz circuit, which can be classified into two parts. The first part next to the varactor chip is characterized by the quasi-coaxial part, while the second part which forms the output embedding circuit is a suspended strip line. The excited second harmonic component is radiated in the unbalanced TEM mode, passes through the quasi-coaxial region between the varactor chip terminal and the input back-short, and then coupled into the output waveguide port with a succession of matching transmission lines. Therefore, the input and output circuit can be designed, respectively. DC is fed in by SMA connector KFD-45, which is connected to a compact hammer type low pass filter, prevents leakage of second harmonic signals and provides an open circuit.

Figure  4.  Structure of the doubler circuit.

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When all different subcircuits have been optimized, the complete doubler circuit is simulated. The seven port $S$-parameters of this simulation are extracted and then combined with a nonlinear diode to model the multiply efficiency, as shown in Fig. 5. This process is repeated for optimum efficiency.

Figure  5.  Global optimization of the doubler.

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3. Experimental results

The doubler circuit substrate is ultrathin quartz with a dielectric constant of 3.78, and thickness of 0.1 mm. The size of the doubler circuit is 7.8 $\times$ 1 $\times$ 0.1 mm$^{3}$ and it is mounted to the block with H20E silver epoxy. The split block is manufactured using brass and electroplated with gold. The split block photograph is presented in Fig. 6.

Figure  6.  Photo of the doubler.

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The doubler measurement setup is presented in Fig. 7. The input pump power of doublers is provided by an Agilent 8257D signal generator, and power is amplified to about 300 mW. The doubler output power is monitored by a PM4 power meter, and frequency is down converted by a harmonic mixer. The simulated and measured efficiency is described as in Fig. 8. The highest measured multiply efficiency is 11.5% at 92.5 GHz, and typical efficiency is 6.0% in 70-100 GHz. The deviation between the measured and simulated efficiency is about 4% at any frequency bandwidth, which may be caused by mismatching between the power amplifier and the doubler. Commonly, an isolator should be utilized to provide accurate measurements, but this is unavailable in our laboratory. As described in Fig. 9, it can be found that the doubler is broadband width and has high output power. The highest measured output power is 29.5 mW at 80 GHz with input power of 275 mW. Power is higher than 15 mW in 76-94 GHz, and higher than 10 mW in 70-96 GHz. From Fig. 10, it can be found the doubler reaches its maximum efficiency response with an input power of 100 mW. With the increasing of input power, the doubler efficiency begins to decrease and the output power keeps a constant level.

Figure  7.  Measurement setup of the doubler.

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Figure  8.  Measured and simulated efficiency of the doubler.

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Figure  9.  Measured performance of the doubler.

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Figure  10.  Efficiency versus pumping power.

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Usually, integrated diode technology is applied for high performance multipliers, where the diode and matching networks are fabricated together for low parasitic parameters and accurate alignment of the diode. The integrated diode becomes increasingly more attractive than discrete diodes and is widely adopted, but this approach is cheap and complex. Table 1 illustrates the performance of VDI commercial doubler products, the VDI represents state-of the art performance in diode frequency mixing and multiplying. Obviously, for our fabricated doubler with discrete diode, the highest measured multiplying efficiency is the same as a VDI's, and the typical efficiency is low off 4%. The doubler efficiency can be even higher if an isolator is applied in the test instruments. If applying integrated diode technology or through our further study we are sure the doubler efficiency will reach the level that the VDI produces by using a domestic manufacturing process.

Table  1.  Performance comparison.

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4. Conclusions

A W-band high output power doubler is discussed and fabricated with a planar Schottky barrier diode. Full-wave analysis is carried out to find diode embedding impedances with a lumped port to model the nonlinear junction. An iterative "divide and combine" design approach is adopted, breaking up the circuit into different parts, and then the different parts are optimized and combined for optimum values. The exported $S$-parameters of the optimized circuit are used for multiplying efficiency discussion. The highest measured output power is 29.5 mW at 80 GHz with input power of 275 mW, and power is higher than 15 mW in 76-94 GHz. The highest measured multiply efficiency is 11.5% at 92.5 GHz, and typical efficiency is 6.0% in 70-100 GHz. The doubler is simple, low cost, high efficiency and high output power which is very attractive for test instruments, frequency sources and W-band transceiver systems.