| Citation: |
Liu Yongwang, Wang Zhigong, Li Wei. 2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit[J]. Journal of Semiconductors, 2007, 28(4): 537-541.
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Liu Y W, Wang Z G, Li W. 2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit[J]. Chin. J. Semicond., 2007, 28(4): 537.
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2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit
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Abstract
A 2.5Gb/s clock and data recovery (CDR) circuit is designed and realized in TSMC’s standard 0.18μm CMOS process.The clock recovery is based on a PLL.For phase noise optimization,a dynamic phase and frequency detector (PFD) is used in the PLL.The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is -111dBc/Hz at 10kHz offset.The rms jitter of the recovered 2.5Gb/s data is 3.3ps.The power consumption is 120mW. -
References
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