1. Introduction

Moore’s law has long motivated scaling in CMOS technology, which has resulted in improvements in speed, power consumption and area. SRAM occupies large chip area and has a high activity factor which gives rise to large dynamic power dissipation. Linear reduction in supply voltage causes reduction of dynamic as well as leakage power dissipation but also reduction in speed. Also, increase in process variability causes an exponential increase in SRAM failure probability. This causes a decrease in write yield and read stability. At high supply voltage dynamic power dominates but at low supply leakage power becomes dominant due to exponential increase in cycle time. As operating frequency and packing density increase, speed, power consumption, noise immunity and low voltage operation become important for on-chip memories. SRAM is highly sensitive to process variations due to use of minimum geometry devices used to achieve high density. Variation from device to device over the same chip or from die to die over different chips can cause device mismatch and cause read stability, readability, write ability and cell stability degradation under data retention voltage (DRV). Moreover, there is a design trade-off between read stability and write stability.

Reduction in supply voltage is a preferred means of controlling leakage in SRAM and since it occupies up to 70% of the chip area^[1], this leads to large savings in overall chip power but directly affects write ability. Over time a lot of new cell architectures^[2–12] have been suggested that improve the stability of cell at the cost of chip area. The 8 T, 9 T, 10 T and 11 T^[3–14] cells aim at improvement of read hold stability with the help of techniques like Schmitt trigger but adversely affect the cell ability to operate at reduced supply voltage and deteriorates below the ability of the basic 6 T cell. Write ability and delay are affected by reduced supply. Write noise margin and write yield are highly affected at scaled supply voltage and process variation makes it worse to an extent that write failure can result.

While 6 T cell shows the best possibility of data retention operation at reduced supply voltage, it suffers from poor stability during read and deteriorated write ability at scaled supply voltages. The WRE 8 T^[8] cell offers improved read SNM of the cell due to separate read path and storage node isolation during read but suffers from the same reduced write noise margin as 6 T cell and added drawback of single bit-line read with inherently long access time. The LP 10 T cell^[10] uses independent read and write paths thus offers no compromise in read and write margin due to access device sizing.

PPN-10 T cell^[3] uses cascaded transistors in each of the back-to-back inverters although offers reduced leakage both from supply and data dependent bit-line leakage but requires higher voltage head-room and thus limits the level to which supply can be scaled. Fig. 1 shows some of the existing SRAM cell topologies available in literature.

Fig. 1(a) shows the basic, widely used 6 T SRAM cell, Fig. 1(b) shows LP 10 T cell, Fig. 1(c) WRE 8 T cell and Fig. 1(d) shows transmission gate assist SRAM cell. The TGA-8 T cell offers improved write ability and write SNM at reduced supply voltage and at the same time provides a read path that is separate from storage nodes and thus offers improved read stability and read SNM.

In this paper, an 11 T SRAM cell is proposed, as shown in Fig. 1(e) which is suitable for boosted-negative bit-line technique and has significant improved write yield and write noise margin. The proposed cell uses transmission gate access transistors, which has improved write strength over the simple NMOS access device. Also, the PMOS device connected in cascade with the left inverter interrupts the supply to weaken the feedback loop and assist in write operation. The read access path does not include the cell nodes and thus exhibits a superior read SNM and read stability.

2. Basic concepts and write-assist techniques

The write operation on 6 T cell with conventional write path, TGA-SRAM cell^[26] and proposed WA 11 T cell with TGA and power supply interrupt are shown in Fig. 2.

In 6 T cell, access devices connected to the cell nodes in the write path perform a see-saw action with two stable states. Let us assume that the node Q holds a logic 0 and node QB holds a logic 1. Changing the state of the cell is possible by applying force to either one side of the see-saw (with increased delay and reduced WSNM) or applying force to both the sides simultaneously (which eases the write operation of SRAM cell equivalent to write improvement). At the start of the write cycle, both the access devices ACL and ACR conduct with equal strength since V_GS-ACL = V_GS-ACR = V_WL. But, as the voltage on the node Q starts to rise, V_GS-ACL starts to decrease resulting in reduced strength of the ACL with ACL reaching cut-off at V_Q = V_WL – V_THN i.e. V_GS-ACL = V_THN. On the other hand, ACR continues to write with the same strength throughout the write operation. Thus, for the 6 T SRAM, write operation is mostly carried-out by the access device connected to node storing a logic ‘1’, which becomes a focus for write-assist.

2.1 Types of write-assist

Write-assist techniques can be divided into following types, namely:

(1) Changing magnitude and or duration for which noise source is applied^[13–16].

(2) Reduction in the latch strength or change in transfer characteristics^{[17, 18]}.

(3) Use of masking or architectural methods.

Numerous publications have devoted a lot of effort on the write-assist techniques like raising global V_DD, reducing theV_DD at cell, raising VSS at cell, word line boosting, boosting voltage at BL and BLB, increasing the strength of access device, weakening of the pull-up device of cell and interrupting to weaken feedback by use of pass transistor or TG.

With raising of the global V_DD, current driving ability of access devices improves. Reduction in V_DD or raising of VSS of the cell during write weaken the latch and write with reduced resistance. Strengthening of access devices with respect to cell by either boosting of the word line (WL) or BL-BLB voltages for weakening of the pull up device of the inverters leads to improved write-ability of the cell.

Reduction in the write bit-line voltage from 0 to −∆V (where ∆V represents magnitude of voltage boost in positive and negative direction) leads to write-ability improvement of the cell by improvement of V_GS and strengthening of the access transistor without any effect over the latch inverters.

WL boosting and latch weakening by either V_DD collapse or VSS raising or by using pass device or TG in the inverter positive feedback loop either lead to poor hold SNM or stability of half-selected cells and require very power-costly control of global V_DD or elaborate control of local V_DD or are unsuitable for reduced supply voltage.

2.2 Negative bit-line assist technique

Application of a negative voltage −∆V instead of ground leads strengthening of the access device connected to cell node storing a high voltage and considerable improvement of write-ability of the cell^[19–25]. Negative bit-line voltage has been produced by the use of C_Boost instead of a separate negative voltage generator charge pump circuit. The C_Boost with the optimum value of charge is applied to the low write bit-line at appropriate time for maximum negative swing in bit-line voltage. For determining the appropriate time, when discharge of the capacitive bit-line to a voltage as close to zero as possible, a separate replica bit-line (capacitance monitor) is used. The replica bit-line, having the same capacitive load C_BL as the actual bit-line and they being connected together, has capacitance of C_BL. The bit-line will discharge completely when the replica bit-line discharges to Gnd.

Design proposed in Ref. [18] uses replica bit-line and replica buffer to determine the time when C_boost should be connected to bit-line. REBL together with the delay block is used to determine the time when boosting capacitor should be connected to the bit-line. The boosting capacitor C_boost is connected to the ground of negative going bit-line to produce a negative voltage on the low going bit-line. Mukhopadhyay et al.^[17] proposed the structure where the C_boost capacitors were coupled to the bit lines BL and BR respectively and they assist appropriate bit-line in reaching a negative voltage level.

3. Proposed WA 11 T cell and boosted negative bit-line technique

In this section first WA 11 T cell is discussed followed by a detailed description of the proposed negative bit-line technique.

3.1 Proposed WA 11 T cell

The proposed WA 11 T cell with nodal voltages and word-line voltages of the cell is shown in Fig. 3. To improve ACL conduction, NMOS access devices on both sides of the cell are replaced by a TG (TPL+TNL and TPR+TNR) on both sides of the cell. This lets us apply write-assist to both sides of the cell and conduction throughout the write operation. As the write operation starts, VGS for the TNL starts to decrease as the voltage builds up over the node Q, but for the TPL, device, V_GS-TPL = V_WBLB – V_WWLB remains constant with rise in VQ and thus, TPL (with its source connected to the bit-line) continues to conduct with maximum strength throughout the write-operation. TG allows write-assist technique to be applied from both sides of the cell simultaneously thus significant improvement in write operation.

NMOS access device is able to conduct only for the duration when its V_GS ≥ V_THN i.e. it will stop conducting when voltage of the cell node rises up to the point that V_GS becomes less than V_THN when the condition for conduction of the NMOS pass device is no longer met. Thus, the pass device writing 1 into the cell node does not conduct for the last remaining part of the write operation and only the NMOS pass device connected logic 0 bit-line conducts and completes the write operation.

In the proposed design, TG is used in place of a simple pass device to ensure rapid charging of cell node where logic 1 is being written since one of the two devices (NMOS or PMOS) will remain in saturation when the other enters triode region. This provides a constant current capability to the TG and ensures faster and uniform charging rate of both the cell nodes throughout the write operation, since in the proposed design, access devices connected to both bit-lines conduct with maximum strength even in the last lean period of the write operation.

Also, focus is on the reduction of the strength of holding the last data during write operation by the SRAM cell. The strength with which SRAM cell holds the last stored value depends on the feedback strength between inverters of the cell. By reducing the feedback strength, a new data value can be written to the cell with a much reduced effort. This is done by interrupting the supply to one of the inverters during the write operation temporarily. Power supply is interrupted to the left inverter using device M_INT with its gate connected to the WWL which will be shown later.

The TG access thus charges the node Q of the cell with maximum strength throughout the write operation. The write delay and dependence over process variability is reduced and write SNM and write yield are improved considerably. This also allows write assist technique to be applied to both sides of the cell i.e. applying force over both sides of the cell simultaneously, which leads to significant write-ability improvement. A pMOS device M1 is connected to the left inverter of the proposed cell whose Gate is connected to write word line, since the power supply to the left inverter is interrupted by M_INT during write operation, which leads to weakening of the feedback strength and significant improvement in write-ability of the proposed cell.

The 6 T cell suffers from poor write ability and the increase of the strength of access devices improves WM and write delay since they have to overcome the positive feedback of inverters. On the other hand, high strength of pass devices leads to a reduced stability of the cell during read and read SNM. To overcome reduced read SNM due to improved strength of access devices, 8 T cell uses a separate read path that does not include the cell nodes. The proposed cell uses the similar structure to provide node isolation during read operation. Thus, the conflict of transistor sizing for access devices is addressed. The proposed cell is isolated from the read bit-line so that maximum stability during read operation is guaranteed.

3.2 Operation of the SRAM cell with the proposed technique

Fig. 4 shows the proposed 11 T array having n-rows and n-columns. Capacitors C_P-Boost and C_N-Boost are used to produce a voltage of V_DD+∆V and −∆V over the bit-lines WBL and WBLB. The replica bit-line consisting of n-rows of 11 T cells are used to determine best time for connecting the boosted positive and negative voltages to the write bit-lines. A capacitance of C_BL is realized by the REBL, which is pre-charged to V_DD before each write operation. REBL is discharged to Gnd using the inverter with WRE signal, which goes high (at start of write operation) as its input.

A voltage sensing circuit is used (M1–M7) where M1, M2, M3 and M4 make back-to-back inverters and M5 and M6 (biased to operate in saturation) form a differential pair that makes the sensing circuit more sensitive than inverter^[19]. WRE connected to gate of M7 enables the voltage sense circuitry (M1–M7), which compares the REBL voltage with Gnd. The dummy bit-line, which is pre-charged to VDD, discharges towards Gnd through the inverter whose input is WRE. The voltage sensing circuit formed by M1 to M7 whose one of the input is connected to the gate of transistor M5 compares the dummy bit-line voltage with gnd.

The input of the NAND gate goes high as soon as dummy bit-line voltage discharges to Gnd. Since the other input to the NAND gate WRE is already high, thus the output goes low, which is applied to the inverter input. As the output of inverter goes high, it comes in series with the C_P-Boost capacitor, which leads to 2V_DDC_P-Boost/C_BL voltage to appear at the WBL through the inverter NW1 when appropriate control signals are activated. Similarly, −VDD × C_N-Boost/C_BL appears at the WBLB during write operation.

Control signal C2 goes high (control C1 goes low) to discharge the WBLB towards Gnd and word-line decoder output WWL and WWLB goes high and low respectively. This interrupts the supply to the left inverter of SRAM cell and turns-on devices of both TGs.

As the voltage over the bit-lines (WBL and WBLB) loaded with C_BIT slowly change towards VDD and Gnd respectively, voltage over input and output nodes of the right inverter begin to change (node QB discharges towards 0 and Q charges towards V_DD). Meanwhile, the boost capacitors C_P-Boost andC_N-Boost are charged using pMOS and nMOS which are ON. Output of voltage sensing circuit RBLE signal goes high when REBL discharges to V_DD/2 which indicates that write bit-lines have also discharged to gnd. Control signal C1 goes high (C2 goes low) and applies the boosted signals (V_DD + ∆V and −∆V) to the WBL and WBLB through the inverters NW1 and NW2 respectively.

· Voltage boosting (on both the cell nodes in opposite directions) increases |V_GS| of TG devices giving them higher strength thus increasing slope of charging of cell nodes. Source of TPL is connected to V_BL = V_DD + ∆V(voltage boosting) and source of TNR connected to V_BLB = −∆V (negative bit-line voltage) during write operation which improves write-ability, write time and WSNM.

· With weakening of the feedback, (due to the left inverter turned off) the rate of charging of node Q and node QB has increased providing an improved WM faster write-ability.

· Use of a new voltage sensing circuit (M1–M7) with more precise timing that improves boosted bit-line voltage (unlike a simple inverter IN^[19]) and helps to lower value of boosting capacitor for the same WM improvement.

· Due to feedback weakening, reduced amount of boosting voltage is required for write improvement, which reduces effect over the half-selected cells of the same column.

· Feedback weakening in WA 11 T reduces voltage boosting amount required for the same WM improvement as earlier suggested techniques to address the issue of reliability degradation of access devices due to increased V_GS (boosted and negative bit-line voltage).

3.3 Mathematical analysis of proposed SRAM cell

The proposed WA 11 T cell during write operation is shown in Fig. 5(a) and its simplified equivalent model of proposed SRAM cell is shown in Figs. 5(b) and 5(c) respectively.

Assuming node Q stores logic ‘0’ and QB stores logic ‘1’, the write operation of cell is modelled in two parts to consider both left and right inverters asymmetrical cell structure.

1. PUR device is modelled as a resistor R_PUR since it operates in triode region. Capacitance at node QB is modelled as C_QB. C_BLB and C_N are the total capacitance of BLB. Since TNR and TPR operate in saturation thus they are modelled as constant current sources.

$${{{C}}_{{\rm{QB}}}}\frac{{\rm{d}}{{V}}_{\rm{QB}}}{{\rm d}t} = {{{I}}_{{\rm{PUR}}}} - {\rm{ }}{{{I}}_{{\rm{TGNR}}}} - {\rm{ }}{{{I}}_{{\rm{TGPR}}}},$$

(1)

$${{{I}}_{{\rm{PUR}}}} = \frac{{{V_{\rm {DD}}} - {V_{\rm {QB}}}}}{{{R_{\rm {PUR}}}}},$$

(2)

$${{{I}}_{{\rm{TNR}}}} = \frac{{{\beta _{\rm TNR}}}}{2}{\left( {{V_{\rm {DD}}} - {V_{\rm {BLB}}} - {V_{\rm {thn}}}} \right)^2},$$

(3)

$${V_{{\rm{QB}}}} = \frac{{\left( {\left| {{b_{\rm{R}}}} \right| - \sqrt {{b_{\rm{R}}}^2 - 4{a_{\rm{R}}}{c_{\rm{R}}}} } \right)Z{{\rm e}^{\frac{{ - {a_{\rm{R}}}{\rm{t}}}}{{\sqrt {{b_{\rm{R}}}^2 - 4{a_{\rm{R}}}{c_{\rm{R}}}} }}}} + \sqrt {{b_{\rm{R}}}^2 - 4{a_{\rm{R}}}{c_{\rm{R}}}} }}{{\left| {2a} \right|\left( {Z{{\rm e}^{\frac{{ - {a_{R.{\rm{t}}}}}}{{{C_{{\rm{QB}}}}\sqrt {{b_{\rm{R}}}^2 - 4{a_{\rm{R}}}{c_{\rm{R}}}} }}}} - 1} \right)}},$$

(4)

where ${{a_{\rm{R}}} = \frac{{ - {\beta _{{\rm{TPR}}}}}}{2}}$ ,

$$\begin{split} & {{b_{\rm{R}}} \,=\,{\beta _{{\rm{TPR}}}}\left| {{V_{{\rm{HP}}}}} \right|-\frac{{\rm{1}}}{{{R_{{\rm{PUR}}}}}}},\\ & {{c_{\rm{R}}} \,=\,\frac{{{V_{{\rm{DD}}}}}}{{{R_{{\rm{PUR}}}}}}-\frac{{{\beta _{{\rm{TPR}}}}}}{{\rm{2}}}{V_{{\rm{THP}}}}^{\rm{2}}-\frac{{{\beta _{{\rm{TNR}}}}}}{{\rm{2}}}{{\left( {{V_{{\rm{DD}}}}-{V_{{\rm{BLB}}}}-{V_{{\rm{THN}}}}} \right)}^{\rm{2}}}},\\ & {Z \,=\,\left| {\frac{{{\rm{2}}{a_{\rm{R}}}{V_{{\rm{DD}}}}{\rm{ + }}{b_{\rm{R}}}{\rm{ + }}\sqrt {{b_{\rm{R}}}^{\rm{2}}{\rm{ - 4}}{a_{\rm{R}}}{c_{\rm{R}}}} }}{{{\rm{2}}{a_{\rm{R}}}{V_{{\rm{DD}}}}{\rm{ + }}{b_{\rm{R}}}-\sqrt {{b_{\rm{R}}}^{\rm{2}}{\rm{ - 4}}{a_{\rm{R}}}{c_{\rm{R}}}} }}} \right|},\\ & {{R_{{\rm{PUR}}}} \,=\,\frac{{\rm{1}}}{{{\beta _{{\rm{PU}}}}{\rm{(}}{V_{{\rm{DD}}}}-{V_{\rm{Q}}}-\left| {{V_{{\rm{THP}}}}} \right|{)}}}},\qquad\qquad \qquad \qquad \quad(5)\end{split}$$

where the details of various parameters are well available in literature.

2. Since supply to left inverter is interrupted, devices node Q are modelled as capacitance C_Q. Devices TNL and TPL are modelled as constant current sources. Boosting capacitance and BL capacitance are represented by C_P and C_BIT at node QB of the cell.

$${C_{\rm{Q}}}\frac{{{\rm{d}}{V_{\rm{Q}}}}}{{{\rm{d}}t}}{\rm{ = }}{I_{{\rm{TNL}}}}{\rm{ + }}{I_{{\rm{TPL}}}},$$

(6)

$${I_{\rm {TGNL}}} = \frac{{{\beta _{\rm {TNL}}}}}{2}{\left( {{V_{\rm DD}} - {V_{\rm thn}}} \right)^2},$$

(7)

$${I_{\rm {TGPL}}} = \frac{{{{\beta}_{\rm {TPL}}}}}{2}{({V_{\rm {BL}}} - |{V_{\rm {thp}}}|)^2},$$

(8)

$${V_{\rm{Q}}} = \frac{{\left( {\left| {{b_{\rm{L}}}} \right| - \sqrt {{b_{\rm{L}}}^2 - 4{a_{\rm{L}}}{c_{\rm{L}}}} } \right)\left( {1 - {{\rm e}^{\frac{{ - {a_{\rm{L}}}{\rm{t}}}}{{{C_{\rm{Q}}}\sqrt {{b_{\rm{L}}}^2 - 4{a_{\rm{L}}}{c_{\rm{L}}}} }}}}} \right)}}{{\left| {2a} \right|\left( {1 - \frac{{|{b_{\rm{L}}}| - \sqrt {{b_{\rm{L}}}^2 - 4{a_{\rm{L}}}{c_{\rm{L}}}} }}{{|{b_{\rm{L}}}| + \sqrt {{b_{\rm{L}}}^2 - 4{a_{\rm{L}}}{c_{\rm{L}}}} }}{{\rm e}^{\frac{{ - {{ a}_{{\rm{L}}{\rm{t}}}}}}{{{C_{\rm{Q}}}\sqrt {{b_{\rm{L}}}^2 - 4{a_{\rm{L}}}{c_{\rm{L}}}} }}}}} \right)}},$$

(9)

where

$$\begin{split}& {a_{\rm{L}}} = \frac{{{\beta _{{\rm{TNL}}}}}}{2},\\& {b_{\rm{L}}}= - {\beta _{{\rm{TNL}}}}{(}{V_{{\rm{DD}}}}{\rm{ - }}{V_{{\rm{THN}}}}{),}\\& {c_{\rm{L}}} = \frac{{{\beta _{{\rm{TNL}}}}}}{{\rm{2}}}{\left( {{V_{{\rm{DD}}}} - {V_{{\rm{THN}}}}} \right)^{\rm{2}}}+ \frac{{{\beta _{{\rm{TPL}}}}}}{{\rm{2}}}{{{(|}}{V_{{\rm{BL}}}}\left| - \right|{V_{{\rm{THP}}}}{|)}^{\rm{2}}}.\end{split}$$

There is an attempt to write node Q, assumed to store logic ‘0’ and logic ‘1’, in BNBL-WA cell. Improvement in the proposed circuit is seen as faster increase of nodal voltage V_Q given by Eq. (9). a_L and c_L are positive whereas b_L is negative. Factor c_L depends on bit-line voltage V_BL, which is increased due to the boosted bit-line technique.

3.4 Improved WM and faster write due to reduction in b_L and increase of c_L

Value of b_L reduces to less than^[19] in the suggested BNBL-WA 11 T. PDL device in operating in triode earlier (as in Ref. [19] with Q = 0 and QB = V_DD) due to interrupted supply to the left inverter, R_PDL becomes infinite, thus 1/R_PDL becomes 0, which causes reduction in b_L. c_L increases with the increase in V_BL (BL voltage boosting) causing an increase in value of c_L. Here, increment and decrement in each of the terms is shown by ↑ and ↓ within parenthesis in numerator and denominator of Eq. (10). b_L reduces whereas c_L increases which causes both first and second terms in the numerator to increase. Whereas, denominator decreases, which shows faster increase in V_Q compared to 8 T cell^[5] and BNBL technique of Ref. [19].

$${V_{\rm Q}} = \frac{{\left( \uparrow \right)\left( {1 - \downarrow \downarrow } \right)}}{{\left| {2a} \right|.\left( {1 - \frac{ \uparrow }{ \downarrow } \downarrow \downarrow } \right)}}.$$

(10)

In 6 T or 8 T^[5] SRAM, charging of node Q is done by the back-to-back inverters, whereas here, due to supply cut-off to the left inverter and breaking of the feedback loop by switching off M_INT, node Q (input to the right inverter) is charged directly by the TPL of TG and QB (output of the right inverter) is discharged directly by TNR of TG without being opposed by feedback of the cell.

· Here, write operation takes place without being resisted by the feedback within cell (like in the conventional 6 T or 8 T cell^[5] or BNBL technique^[19]).

· Boosting of the bit-line voltage causes increase in strength of access devices thus a faster charging of node Q and discharge of node QB giving an improved write margin and write-ability to the proposed design than Ref. [19].

4. Results and discussions

Simulation at 45 nm CMOS technology was done to compare BNBL-WA 11 T, WRE 8 T, conventional 6 T and LP 10 T cells.

Fig. 6(a) shows plot of the word-line voltage versus nodal voltages for dc analysis of BNBL WA 11 T and TGA 8 T cells.

The simulation was done for BNBL WA 11 T and TGA 8 T cells at supply voltage of 0.3 V and boosting of 9% and 20% applied to the cell respectively. Write-margin is calculated as the difference between 90% of the final word-line voltage (i.e. 0.27 V) and cross-over point of nodal voltages. The WM of 146 and 35 mV for BNBL WA 11 T and TGA 8 T cells respectively was obtained. An improvement of 70% in WM compared to Ref. [5] provided improved write-ability with reduced amount of boosting required. Fig. 6(b) shows parametric sweep analysis for read operation of WA-11 T for supply voltages of 0.15, 0.4, and 0.65 V and temperatures of −125, 260, and 650 °C respectively.

4.1 Comparison of write-assist techniques

In this section, we compare BNBL, NBL, BBL (boosted bit-line) and no write-assist techniques when applied to the proposed WA 11 T SRAM. Ground boosting and VDD collapse are not included since these techniques have inherent drawbacks. Boosting ground voltage leads to reduced V_DS of access devices connected Q and increases trip point of the right hand side inverter. On the other hand, cell VDD collapse technique decreases VDS of access device connected to QB and increases the trip point of the right inverter.

Write margin of the WA 11 T cell has been calculated using different techniques^[24]. Since most of the suggested write techniques depend on low-going bit-line connected to side of SRAM cell, most techniques consider low-going bit-line for WM calculation. To take into consideration the effect of both bit-lines we consider write word-line voltage sweep (WWL from 0 V to V_DD and WWLB from V_DD to 0 V are swept together) and consider the point at which flipping of the state of inverters connected to the cell nodes occurs. We consider WM as the difference between points when write word-lines achieve 70% of their final value and the cross over points of the nodal voltages^{[24, 25]}.

In Fig. 7, DC analysis has been performed for word-line voltage sweep from 0 to V_DD and negative bit-line, boosted bit-line, boosted negative bit-line and with no write-assist are applied to the WA-11 T cell. WM was found as A, B, C and D for BNBL, no-assist, NBL and BBL respectively. Here WM is defined as the difference in voltage between nodal cross-over point and 70% of maximum word-line voltage and gives the measure of margin against write failure.

In the proposed design (Fig. 8, use of WA-11 T with BNBL) with a V_DD of 0.3 V, boosted and negative voltage of 0.325 V and −0.025 V, i.e. 9% boosting is used. WM for BNBL, no write-assist, NBL and BBL were found to be 0.095, 0.05, 0.066, and 0.03 V respectively. BNBL provides 47%, 31%, and 68.4% improvement in WM (mentioned in Table 1) with respect to no write-assist, NBL and BBL respectively.

Thus, BNBL was found to be the best write-assist technique to improve write margin. With less than half of the boosting and negative bit-line voltages applied (considering 20% boosting at VDD of 1V used in Ref. [19]), much higher improvement in WM was obtained. This is attributed to the collapse in the feedback strength within cell which enables faster writing into the proposed WA 11 T cell.

The proposed technique requires much smaller value of boosting capacitor and the area overhead for the same improvement in WM as Refs. [17–19]. Also, with the reduction in value of boosting, the reliability issues associated with access devices have been addressed, which nag other suggested write-assist techniques based on boosted and negative bit-line voltages.

Fig. 9 shows simulation of write margin for BNBL WA 11 T cell for all four process corners i.e. FF, FS, SF and SS. Table 2 gives the write margin and write-time obtained for the WA 11 T cell.

Write margin is calculated with the difference in voltage between point when write word-lines reach 70% of VDD to the nodal voltage cross-over point of cell. Write margin for FF, FS, SF and SS process corners were found to be 0.099, 0.076, 0.054, and 0.016 V respectively. The write margin for FF process corner is 1.26 ×, 1.78 × the FS and SF process corner margins. Write-time for FF, FS, SF and SS were found to be 8.9, 17.2, 20.6, and 127 ps respectively. Write time for FF was found to be only 51.8% and 43% of FS and SF process corners respectively.

Fig. 10 is supply voltage versus RSNM for 6 T, WA 11 T, LP 10 T and WRE 8 T cells. Read noise margin for WA 11 T is also significantly higher than the other cell in the supply voltage range of 0.49 V to 0.89 V. RSNM was found to be 1.2 ×, 1.42 × and 1.24 × higher than the WRE8 T, LP10 T and 6 T cells respectively, while LP10 T has the least RSNM and the same trend is followed with the entire range of supply voltage.

In Fig. 11, the variation of read access device aspect ratio from 1.125 to 14 showed a constant RSNM for the WA-11 T cell whereas a lot of variation in RSNM for all the other cells. An improvement of 2.09 ×, 5.24 × and 2.53 × as compared to WRE8 T, LP10 T and 6 T cells respectively at aspect ratio of 1.125 for read access device was observed.

Fig. 12 plots supply voltage varied between 0.41 and 1 V versus WSNM for WA 11 T, WRE 8 T, conventional 6 T and LP 10 T cells. The WSNM for WA 11 T was found to be improved by 2.4 ×, 5.36 × and 4.1 × compared to WRE8 T, LP10 T and 6 T respectively at supply voltage of 0.4 V.

Fig. 13 M_INT device width versus SNM is plotted for read, write and hold. Write SNM shows a gradual reduction with increase in M_INT width. This reduction is due to increase in strength of feedback with width of M_INT, which makes it harder to write.

Fig. 14 plots write access devices of TG channel ratio varied from 1.125 to 14 and WSNM was found to be constant for BNBL-WA 11 T and WRE8 T cells and 2×, 5.02× and 2.52× higher than WRE8 T, LP10 T and 6 T respectively.

Variation of leakage power with supply voltage is shown in Fig. 15. Variation of write power dissipation with supply voltage from 0.41 to 1 V has been plotted on a logarithmic scale in Fig. 16. There is a 24×, 6.3× and 46.6× times reduction in the write power for BNBL-WA 11 T at 0.41 V supply compared to WRE8 T, LP10 T and 6 T respectively. The write power increases more rapidly than the other cells but continues to stay lowest among the four cell for BNBL-WA11 T from supply voltage of 0.41 to 0.55 V, then exceeds the power for LP10 T cell but is still lower than WRE8 T and 6 T cells. The WRE8 T still continues to consume power lower than the 6 T cell.

Variation of read power with supply voltage shown in Figs. 17 and 18 shows change in write-time with supply voltage for WA 11 T, LP 10 T, WRE 8 T and 6 T cells. Write-times are 23, 112, 63 and 11 ps i.e. an improvement of 79%, 63% whereas a deterioration by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively.

Fig. 19 shows the relative WSNM, RSNM, HSNM and leakage power dissipation in microwatts for all the four cells. It is found that WSNM for WA 11 T is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. RSNM for WA 11 T is better than 6 T and WRE8 T but lower than LP10 T. RSNM for WA 11 T is 1.21×, 1.16× and 1.45× WRE8 T, LP10 T and 6 T but only 0.77× that of LP10 T. HSNM is equal to RSNM and 0.7×, 1.45× and 0.97× that for WRE8 T, LP10 T and 6 T respectively. HSNM for the WA 11 T is little less than the WRE8 T and 6 T cells but is more than the LP10 T cell. Leakage power is least for the WA 11 T cell. The leakage power for WA 11 T is only 0.936×, 0.83× and 0.49× WRE8 T, LP10 T and 6 T cells respectively. Fig. 20 shows a comparison of read power, write power and leakage power for different cell topologies selected.

4.2 Write Time

Write time is the difference in time between asserting word-lines and storage nodes attain 90% of their final values measured. In the proposed write assist technique, WL signals are applied at the beginning of write cycle, which discharges cell node along with appropriate bit-line. The write-assist technique can be divided into two parts: (a) discharging the bit-lines and the cell (keeping write WL on) to Gnd in time ‘t’ (t₀ < t < t₁) and (b) applying boosting voltages (positive and negative) to the bit-lines at time ‘t’ (t > t₁).

5. Conclusions

This paper proposes a new write-assist technique where boosted voltage is applied to one of the bit-lines and negative voltage is applied to the other bit-line. This strengthens the write access devices. This is used with a proposed WA 11 T SRAM cell where power supply to one of the inverters is interrupted during write operation that weakens the feedback strength. This improves write-ability, WSNM and write delay at low supply voltage to minimize leakage power.