J. Semicond. > 2024, Volume 45 > Issue 6 > 061701, doi: 10.1088/1674-4926/23120051
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Complementary memtransistors for neuromorphic computing: How, what and why

Qi Chen1, Yue Zhou2, Weiwei Xiong1, Zirui Chen3, 1, Yasai Wang4, 1, Xiangshui Miao1 and Yuhui He1,

+ Author Affiliations

 Corresponding author: Yuhui He, heyuhui@hust.edu.cn

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Abstract: Memtransistors in which the source−drain channel conductance can be nonvolatilely manipulated through the gate signals have emerged as promising components for implementing neuromorphic computing. On the other side, it is known that the complementary metal-oxide-semiconductor (CMOS) field effect transistors have played the fundamental role in the modern integrated circuit technology. Therefore, will complementary memtransistors (CMT) also play such a role in the future neuromorphic circuits and chips? In this review, various types of materials and physical mechanisms for constructing CMT (how) are inspected with their merits and need-to-address challenges discussed. Then the unique properties (what) and potential applications of CMT in different learning algorithms/scenarios of spiking neural networks (why) are reviewed, including supervised rule, reinforcement one, dynamic vision with in-sensor computing, etc. Through exploiting the complementary structure-related novel functions, significant reduction of hardware consuming, enhancement of energy/efficiency ratio and other advantages have been gained, illustrating the alluring prospect of design technology co-optimization (DTCO) of CMT towards neuromorphic computing.

Key words: complementary memtransistor, neuromorphic computing, reward-modulated spike timing-dependent plasticity, remote supervise method, in-sensor computing



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Fig. 1.  (Color online) Comparison of the nonvolatile conductance tuning in memristor (a) and in memtransistor (b) and the application of memtransistor in spiking neural network for concurrent forwarding and updating (c)[12].

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Fig. 2.  (Color online) Complementary memtransistors: How, what and why?

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Fig. 3.  (Color online) Various mechanisms/materials for realizing nonvolatile gate-tuning of channel conductance. (a) HfZrOx ferroelectric layer as gate dielectrics[13]; (b) van der Waals ferroelectric semiconductor In2Se3 as channel material[14]; (c) floating gate[15]; (d) charge trapping layer[16]; (e) ion migration[17]; (f) filamentary[18]; (g) phase-change materials Ge15Sb85&Sb as channel[19]; (h) van der Waals heterojunctions[20].

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Fig. 4.  (Color online) Complementary tuning of channel conductance in CMT made by p-channel (a) and n-channel (b)[34]. (c) and (d) The nonvolatile conductance tuning through gate voltage pulses realized in the p- and n-channel MT, where the dependence on the initial conductance and pulse heights are illustrated. (e) and (f) Opposite long-term potentiation (LTP) and depression (LTD) realized in the two devices of CMT.

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Fig. 5.  (Color online) STDP and anti-STDP realized with CMT. (a) and (b) The synaptic weight update ∆w as a function of the timing difference (tpre−tpost) between pre- and post-synaptic spikes according to spike timing-dependent plasticity (STDP) and anti-STDP rule; (c) p-channel and n-channel MT to realize STDP & anti-STDP; (d) spike waveform design for pre- and post-synaptic neuronal firing to realize STDP and anti-STDP; (e) the measured STDP in p-type MT and anti-STDP in n-type CMT[42].

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Fig. 6.  (Color online) The principle of remote supervised method (a) and implementing it with STDP and anti-STDP pair (b) and (c).

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Fig. 7.  (Color online) Implementing ReSuMe with CMT-based circuit (a)[12, 34, 42] or with ordinary MT-based one (b), and the signal flowchart (c)[34].

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Fig. 8.  (Color online) Refresh operation in CMT designed for maintaining symmetry (a), the flowchart (b) and test on MNIST benchmark (c)[34].

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Fig. 9.  (Color online) The principle (a)[49], biological evidence (b) and signal flowchart of artificially designed R-STDP (c)[50].

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Fig. 10.  (Color online) Implementing R-STDP with CMT[51]. (a) Cell and circuit design. (b) CMT made up WSe2 channel and PVDF ferroelectric for R-STDP implementation. (c) and (d) The measured conductance tuning by positive (reward) and negative (punishment) feedback signals. (e) The cart-pole benchmark for reinforcement learning. (f) Single-layer SNN design for cart-pole test. (g) and (h) The synaptic maps of the output neurons after R-STDP training obtained through network-level simulation.

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Fig. 11.  (Color online) The principle of dynamic vision sensing with optoelectronic CMT (a)[56, 57] and experimental results (b).

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Fig. 12.  (Color online) Neuromorphic computing enabled by modulable photoelectric response in optoelectronic CMT[56]. (a) Optoelectronic CMT made by incorporating WSe2 channel, split-gate (Au) and charge trapping layers (HfO2); (b) the transfer characteristics of the fabricated optoelectronic MT, where the inset shows schematically the gate voltage induced changes in the charge trapping layer and the channel; (c) by setting the split gates VG1 and VG2 at ±6 V, the measured output characteristics of the optoelectronic MT; (d) the photocurrent measured under incident light (λ = 520 nm) with increasing power, where the channel is set as PN or NP junction; (e) the short-circuit photocurrent ISC as a function of the power density of the input light where the channel is switched between NP and PN junction by the split-gate; (f) the coefficient of the photocurrent response R as a function of two series of SET/RESET programming voltage pulses, one series of split gate pulses with VG1 = −VG2 = −6 V with pulse widths of 5 μs and the other with VG1 = −VG2 = +6 V.

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Fig. 13.  (Color online) Motion recognition realized with a 128 × 128 array of CMT cells[56]. (a) Sketch of the event-driven SNN pixel array and the magnified view of circuit diagrams of a typical pixel and an output neuron; (b) the output photocurrent Itotal in respond to motion sensed by pixel array.

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Table 1.   Mechanisms for nonvolatile conductance tuning in memtransistors and the key indices of performance of them.

Mechanism Channel
layer		 Memory
layer		 Operating
voltage (V)		 On/off
ratio		 Endurance
(cycles)		 Retention
(s)		 Speed
(s)		 Ref
Ferroelectric InZnOx HfZrOx <5 ~104 >108 N/A <10-6 [13]
Ferrosemi-conductor InSe 4 >106 >100 >104 2 × 10−7 [14]
Charge trapping BP-ReS2 POx 4 106 N/A 50 10−3 [16]
Floating gate MoS2 Gr 6 >105 30 N/A 10−4 [15]
Ion migration WO3 8.5/10 20 >105 ~102 N/A [17]
Filamentary MoS2&SnOx 5 ~108 106 N/A N/A [18]
Phase change Ge15Sb85&Sb N/A 102 1015 N/A N/A [19]
vdW hetero-junctions ReSe2&graphene N/A 103 103 ~104 N/A [20]
DownLoad: CSV

Table 2.   Comparison of various hardware approach to implementing ReSuMe[34].

Features CMT[34] Si-ferroelectric FET[46] Ferroelectric FinFET[47] RRAM[48]
Supervised circuit Not required Required Required Required
Accuracy (%) 86 90 41 73
Energy (μJ) 4.7 980 1500 870
Area (μm2) 100 1190 3657 1072
Latency (s) 2 × 104 3.36 × 104 5.6 × 107 4.2 × 108
DownLoad: CSV

Table 3.   Comparison of various hardware approaches to implementing R-STDP.

Features Supervised circuit Application Energy Area
CMT[51] Not required Image pattern(X/O) recognition task 32 pJ 100 μm2
4T1M[52] Not required Cart-pole task N/A N/A
DownLoad: CSV
[1]
Chua L. Memristor-The missing circuit element. IEEE Transactions on Circuit Theory, 1971, 18(5), 507 doi: 10.1109/TCT.1971.1083337
[2]
Strukov D B, Snider G S, Stewart D R, et al. The missing memristor found. Nature, 2008, 453(7191), 80 doi: 10.1038/nature06932
[3]
Jo S H, Chang T, Ebong I, et al. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett, 2010, 10(4), 1297 doi: 10.1021/nl904092h
[4]
Alibart F, Zamanidoost E, Strukov D B. Pattern classification by memristive crossbar circuits using ex situ and in situ training. Nat Commun, 2013, 4, 2072 doi: 10.1038/ncomms3072
[5]
Yao P, Wu H, Gao B, et al. Face classification using electronic synapses. Nat Commun, 2017, 8, 15199 doi: 10.1038/ncomms15199
[6]
Wang Z R, Joshi S, Savel’ev S, et al. Fully memristive neural networks for pattern classification with unsupervised learning. Nat Electron, 2018, 1(2), 137 doi: 10.1038/s41928-018-0023-2
[7]
Cai F X, Correll J M, Lee S H, et al. A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations. Nat Electron, 2019, 2(7), 290 doi: 10.1038/s41928-019-0270-x
[8]
Yao P, Wu H Q, Gao B, et al. Fully hardware-implemented memristor convolutional neural network. Nature, 2020, 577(7792), 641 doi: 10.1038/s41586-020-1942-4
[9]
Sangwan V K, Lee H S, Bergeron H, et al. Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide. Nature, 2018, 554(7693), 500 doi: 10.1038/nature25747
[10]
Yan X D, Qian J H, Sangwan V K, et al. Progress and challenges for memtransistors in neuromorphic circuits and systems. Adv Mater, 2022, 34(48), e2108025 doi: 10.1002/adma.202108025
[11]
Nishitani Y, Kaneko Y, Ueda M. Supervised learning using spike-timing-dependent plasticity of memristive synapses. IEEE Trans Neural Netw Learn Syst, 2015, 26(12), 2999 doi: 10.1109/TNNLS.2015.2399491
[12]
Chen Y Y, Zhou Y, Zhuge F W, et al. Graphene–ferroelectric transistors as complementary synapses for supervised learning in spiking neural network. NPJ 2D Mater Appl, 2019, 3(1), 31 doi: 10.1038/s41699-019-0114-6
[13]
Kim M K, Kim I J, Lee J S. CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory. Sci Adv, 2021, 7(3), eabe1341 doi: 10.1126/sciadv.abe1341
[14]
Liao J Y, Wen W, Wu J X, et al. Van der waals ferroelectric semiconductor field effect transistor for in-memory computing. ACS Nano, 2023, 17(6), 6095 doi: 10.1021/acsnano.3c01198
[15]
Wang H, Lu Y L, Liu S B, et al. Adaptive neural activation and neuromorphic processing via drain-injection threshold-switching float gate transistor memory. Adv Mater, 2023, 35, 2309099 doi: 10.1002/adma.202309099
[16]
Xiong X, Kang J Y, Hu Q L, et al. Reconfigurable logic-in-memory and multilingual artificial synapses based on 2D heterostructures. Adv Funct Materials, 2020, 30(11), 1909645 doi: 10.1002/adfm.201909645
[17]
Onen M, Emond N, Wang B M, et al. Nanosecond protonic programmable resistors for analog deep learning. Science, 2022, 377(6605), 539 doi: 10.1126/science.abp8064
[18]
Yan X D, Ma J H, Wu T, et al. Reconfigurable Stochastic neurons based on tin oxide/MoS2 hetero-memristors for simulated annealing and the Boltzmann machine. Nat Commun, 2021, 12(1), 5710 doi: 10.1038/s41467-021-26012-5
[19]
Sarwat S G, Kersting B, Moraitis T, et al. Phase-change memtransistive synapses for mixed-plasticity neural computations. Nat Nanotechnol, 2022, 17(5), 507 doi: 10.1038/s41565-022-01095-3
[20]
Shania R, Honggyun K, Farooq K M, et al. Tunable resistive switching of vertical ReSe2/graphene hetero-structure enabled by Schottky barrier height and DUV light. J Alloys Compd, 2021, 855, 157310 doi: 10.1016/j.jallcom.2020.157310
[21]
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    Received: 28 December 2023 Revised: 17 February 2024 Online: Accepted Manuscript: 06 March 2024Uncorrected proof: 08 March 2024Published: 15 June 2024

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      Article Navigation >  Journal of Semiconductors  > 2024  >  45(6): 061701
      Qi Chen, Yue Zhou, Weiwei Xiong, Zirui Chen, Yasai Wang, Xiangshui Miao, Yuhui He. Complementary memtransistors for neuromorphic computing: How, what and why[J]. Journal of Semiconductors, 2024, 45(6): 061701. doi: 10.1088/1674-4926/23120051 Q Chen, Y Zhou, W W Xiong, Z R Chen, Y S Wang, X S Miao, and Y H He, Complementary memtransistors for neuromorphic computing: How, what and why[J]. J. Semicond., 2024, 45(6), 061701 doi: 10.1088/1674-4926/23120051Export: BibTex EndNote
      Citation:
      Qi Chen, Yue Zhou, Weiwei Xiong, Zirui Chen, Yasai Wang, Xiangshui Miao, Yuhui He. Complementary memtransistors for neuromorphic computing: How, what and why[J]. Journal of Semiconductors, 2024, 45(6): 061701. doi: 10.1088/1674-4926/23120051

      Q Chen, Y Zhou, W W Xiong, Z R Chen, Y S Wang, X S Miao, and Y H He, Complementary memtransistors for neuromorphic computing: How, what and why[J]. J. Semicond., 2024, 45(6), 061701 doi: 10.1088/1674-4926/23120051
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      Complementary memtransistors for neuromorphic computing: How, what and why

      doi: 10.1088/1674-4926/23120051
      • 1.

        School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China

      • 2.

        Department of Electrical and Computer Engineering, University of California, San Diego, USA

      • 3.

        Dipartimento di Elettronica e Informazione and IU.NET, Politecnico di Milano, Milano, Italy

      • 4.

        Department of Applied Physics, Hong Kong Polytechnic University, Hong Kong, China

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      • Qi Chen got her Bachelor and Master’s degrees in 2009 and 2011 from School of Electrical Engineering, Wuhan University. Now she is an engineer at School of Integrated Circuits, Huazhong University of Science and Technology, responsible for teaching and experiments on microelectronics
      • Yue Zhou got her Bachelor’s and Ph.D in 2018 and 2023 from School of Integrated Circuits, Huazhong University of Science and Technology. During Ph.D study, she published several first-author papers on Nature Electronics, International Electronic Device Meeting (IEDM), and received the 1st class Scholarship on Integrated Circuits by Chinese Institute of Electronics. She is now a post-doc at University of California, San Diego, USA
      • Yuhui He got his Bachelor’s and Ph.D in 2003 and 2009 from Department of Microelectronics, Peking University. He is now a professor at School of Integrated Circuits, Huazhong University of Science and Technology. His research focuses on nanoelectronic devices and circuits for neuromorphic computing
      • Corresponding author: heyuhui@hust.edu.cn
      • Received Date: 2023-12-28
      • Revised Date: 2024-02-17
        • Available Online: 2024-03-06

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