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Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies

Yu Song1, 2, 3, Pengfei Jiang1, 2, , Pan Xu1, 2, 3, Xueyang Peng1, 2, 3, Qianqian Wei1, 2, 3, Qingyi Yan1, 2, 3, Wei Wei1, 2, Yuan Wang1, 2, Xiao Long1, 2, Tiancheng Gong1, 2, Yang Yang1, 2, Eskilla Venkata Ramana4 and Qing Luo1, 2,

+ Author Affiliations

 Corresponding author: Pengfei Jiang, jiangpengfei@ime.ac.cn; Qing Luo, luoqing@ime.ac.cn

DOI: 10.1088/1674-4926/24100010CSTR: 32376.14.1674-4926.24100010

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Abstract: The novel HfO2-based ferroelectric field effect transistor (FeFET) is considered a promising candidate for next-generation nonvolatile memory (NVM). However, a series of reliability issues caused by the fatigue effect hinder its further development. Therefore, a comprehensive understanding of the fatigue mechanisms of the device and optimization strategies is essential for its application. The fundamental mechanism of the fatigue effect is attributed to charge trapping and trap generation based on the current studies, and the underlying causes, occurrence locations and specific impacts are analyzed in this review. In particular, the asymmetric trapping/detrapping of electrons and holes, as well as the relationship between the ferroelectric (FE) polarization and charge trapping, are given particular attention. After categorizing and summarizing the current progress, we propose a series of optimization strategies derived based on the fatigue mechanisms.

Key words: FeFET, fatigue, charge trapping, trap generation



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Fig. 1.  (Color online) Energy band diagrams of Si FeFETs under (a) a positive gate voltage with down-state polarization and (b) a negative gate voltage with up-state polarization[49].

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Fig. 2.  (Color online) (a) Electron distribution in the n-FeFET. (b) Hole distribution in the p-FeFET[49].

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Fig. 3.  (Color online) Estimation of the MW: (a) FeFET without electron trapping; (b) nonferroelectric MOSFET with electron trapping; (c) FeFET with electron trapping[49].

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Fig. 4.  (Color online) (a) Charge trapping in FeFETs during P/E pulses along with the resultant changes in the MW and ION/IOFF ratio; (b) polarization switching cycles of n-FeFETs with repeating cycles of electron trapping and recombination at positive and negative gate voltage, respectively; (c) read-after-write delay in n-FeFETs[49].

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Fig. 5.  (Color online) (a) Behavior of electrons and holes in FeFETs during the application of a negative gate voltage; (b) the floating body structure prevents holes from being injected into the gate stack[30].

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Fig. 6.  (Color online) (a) Positive erase pulse tends to cause charge trapping and generation of border traps in HfO2 near the IL, and (b) negative program pulse tends to cause more interface trap generation at the IL/Si interface[32].

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Fig. 7.  (Color online) Trap generation leading to SS degradation.

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Fig. 8.  (Color online) Optimization strategies[16].

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Fig. 9.  (Color online) General block diagram of the content. This review examines the two primary mechanisms of FeFET fatigue: charge trapping and trap generation, from the aspects of underlying causes, locations and impacts, in which the asymmetric trapping/detrapping of electrons and holes and the relationship between FE polarization and charge trapping are highlighted. Based on the aforementioned mechanisms, the key to optimizing the device performance is concluded to be the suppression of trapping and passivation of defects. In light of this, targeted optimization strategies are proposed, and existing optimization results in terms of both the operating conditions and the gate stack structure are summarized.

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    Received: Revised: Online: Accepted Manuscript: 08 February 2025Uncorrected proof: 18 February 2025

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      Article Navigation >  Journal of Semiconductors  > 2025  > Uncorrected proof
      Yu Song, Pengfei Jiang, Pan Xu, Xueyang Peng, Qianqian Wei, Qingyi Yan, Wei Wei, Yuan Wang, Xiao Long, Tiancheng Gong, Yang Yang, Eskilla Venkata Ramana, Qing Luo. Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/24100010 ****Y Song, P F Jiang, P Xu, X Y Peng, Q Q Wei, Q Y Yan, W Wei, Y Wang, X Long, T C Gong, Y Yang, E V Ramana, and Q Luo, Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies[J]. J. Semicond., 2025, 46(6), 061302 doi: 10.1088/1674-4926/24100010
      Citation:
      Yu Song, Pengfei Jiang, Pan Xu, Xueyang Peng, Qianqian Wei, Qingyi Yan, Wei Wei, Yuan Wang, Xiao Long, Tiancheng Gong, Yang Yang, Eskilla Venkata Ramana, Qing Luo. Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/24100010 ****
      Y Song, P F Jiang, P Xu, X Y Peng, Q Q Wei, Q Y Yan, W Wei, Y Wang, X Long, T C Gong, Y Yang, E V Ramana, and Q Luo, Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies[J]. J. Semicond., 2025, 46(6), 061302 doi: 10.1088/1674-4926/24100010
      shu

      Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies

      DOI: 10.1088/1674-4926/24100010
      CSTR: 32376.14.1674-4926.24100010
      • 1.

        Key Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing 100029, China

      • 2.

        Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

      • 3.

        University of Chinese Academy of Sciences, Beijing 101408, China

      • 4.

        I3N-Aveiro, Department of Physics, University of Aveiro, Aveiro, 3810 193, Portugal

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      • Yu Song got her BEng from Beijing University of Technology in 2024. Now she is a graduate student at University of Chinese Academy of Sciences. Her research focuses on the hafina-based ferroelectric memory, including reliability research and Integration technology
      • Pengfei Jiang got his PhD degree from the Institute of Microelectronics, Chinese Academy of Sciences (IMECAS) in 2022. He is currently a research associate in the Key Laboratory of Fabrication Technologies for Integrated Circuits in IMECAS. His research focuses on the Hafina based ferroelectric memory, including materials, devices and high-density integration technology
      • Qing Luo received the Ph.D. degree in microelectronics from University of Chinese Academy of Sciences, Beijing, China, in 2017. He is currently a professor with the Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China. His research fields include hafnia-based ferroelectric memory and 3-D integration techniques of RRAM
      • Corresponding author: jiangpengfei@ime.ac.cn; luoqing@ime.ac.cn
      • Available Online: 2025-02-08

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