Yu Song got her BEng from Beijing University of Technology in 2024. Now she is a graduate student at University of Chinese Academy of Sciences. Her research focuses on the hafina-based ferroelectric memory, including reliability research and Integration technology.
Pengfei Jiang got his PhD degree from the Institute of Microelectronics, Chinese Academy of Sciences (IMECAS) in 2022. He is currently a research associate in the Key Laboratory of Fabrication Technologies for Integrated Circuits in IMECAS. His research focuses on the Hafina based ferroelectric memory, including materials, devices and high-density integration technology.
Qing Luo received the Ph.D. degree in microelectronics from University of Chinese Academy of Sciences, Beijing, China, in 2017. He is currently a professor with the Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China. His research fields include hafnia-based ferroelectric memory and 3-D integration techniques of RRAM.1. Introduction
The discovery of ferroelectricity in Si-doped HfO2 has initiated a new era of research on ferroelectric field effect transistors (FeFETs)[1−7]. With their exceptional compatibility with complementary metal‒oxide‒semiconductor (CMOS) technology, low power consumption, rapid write/read speeds, high scalability and mature manufacturing processes, HfO2-based FeFETs have become highly promising novel nonvolatile memory technologies[3, 6, 8−14], showing significant potential in fields such as cloud computing, artificial intelligence (AI), and the internet of things (IoT). However, the fatigue effect of HfO2-based FeFETs has significantly impeded their commercialization and widespread application[2, 15, 16]: (1) the memory window (MW) narrows with increasing number of program/erase (P/E) cycles; (2) the threshold voltage (Vth) shifts cause write-after-read delay; (3) the ION/IOFF ratio decreases due to the Vth shift and subthreshold slope (SS) degradation; and (4) the gate leakage current increases, resulting in a proportional increase in the static power consumption and ultimately leading to device failure. The endurance limit of current HfO2-based FeFETs is typically constrained to 104−106 cycles[17−22]; although some studies have indicated the potential for enhancement up to over 109 cycles[23, 24], the endurance remains insufficient for memory and in-memory computing applications[25]. Therefore, elucidating the precise mechanism underlying the fatigue of FeFETs to implement targeted optimizations and improvements is imperative.
The FE layer is the core of a FeFET; thus, the endurance degradation of the FE layer must first be considered. The endurance issues associated with HfO2-based FE films are now widely acknowledged to be primarily attributable to the presence of defects (such as oxygen vacancies) generated during the electrical cycling process, resulting in a phase transition from the FE orthorhombic phase (o-phase) to nonferroelectric phases, such as the tetragonal phase (t-phase) and monoclinic phase (m-phase), as well as FE domain pinning, leading to polarization degradation and even dielectric breakdown[26, 27]. Nevertheless, fatigue of the HfO2-based FE layer typically occurs after 105 cycles, suggesting that fatigue of the FE layer may not be the primary factor in FeFETs. Yurchuk et al.[28] employed metal/ferroelectric/insulator/semiconductor (MFIS) FeFETs and metal/ferroelectric/metal (MFM) capacitors with identical FE layers for endurance testing. It was found that fatigue of the MFM capacitor started degrading after 109 cycles while FeFETs started degrading after 104 cycles. They also observed a correlation between increased interfacial trap density and increased gate leakage during cycling, inferred from the observed increase in charge pumping current. The most apparent distinction between MFM capacitors and FeFETs is the presence of a metal silicate interlayer (IL), thus the degradation of the gate stack, particularly the IL, may be the primary contributor to fatigue of HfO2-based FeFETs. Most studies have demonstrated that charge trapping and trap generation are pivotal factors[5, 6, 15, 16, 29−35].
In this paper, we provide a systematic review of the recent research advances in the fatigue effects of HfO2-based FeFETs. By analyzing and comparing various research methodologies and experimental outcomes in-depth, we seek to elucidate the underlying causes, locations and impacts associated with the two primary mechanisms of FeFET fatigue: charge trapping and trap generation. Furthermore, our research concentrates on the asymmetric behavior of electrons and holes involved in charge trapping, as well as the interrelation between FE polarization and charge trapping. Ultimately, targeted optimization strategies are proposed, and the latest optimization achievements in terms of both the operating conditions and the gate stack structure are summarized. Based on this review, more systematic theoretical support can be provided for the design and optimization of future FeFET devices.
2. Fatigue mechanisms—charge trapping
Owing to the large spontaneous polarization of HfO2-based FE materials (10−30 µC/cm2) and the dielectric constant mismatch between the FE layer and IL, the electric field on the SiO2 IL may reach 30−90 MV/cm, which is much greater than its breakdown field (<15 MV/cm). As a result, severe charge trapping/detrapping behavior occurs during the P/E process[36, 37]. HfO2 is known to exhibit a high density of intrinsic defects (1012−1014 cm−2)[38], most of which are oxygen vacancies[39−41] and interstitial oxygen atoms[39, 41, 42], which act as electron traps[39] or hole traps[43]. Ni et al.[44] demonstrated that oxygen vacancies act as shallow electron traps, whereas interstitial oxygen atoms act as hole traps. The main methods currently used to analyze the charge trapping/detrapping behavior of FeFETs include the quasi-static (QS) C−V technique[35, 45], Hall measurement[16, 45], fast charge centroid analysis[34], in situ Vth measurement[31], single-pulse ID−VG measurement[46], and split I−V measurement[30]. These studies offer valuable insights into the intricate physical dynamics of charge trapping/detrapping during fatigue, as well as the specific mechanism by which charge trapping/detrapping degrades the device performance.
2.1 Charge trapping position
Determining the locations where charge trapping occurs is highly important for the design and optimization of FeFETs, which allows targeted material and structural modifications to reduce adverse effects and thereby improve the endurance. From the standpoint of the physical location, Ni et al.[44] quantified the Vth shift arising from electron/hole trapping near the FE/IL interface induced by the P/E pulse. Their findings indicated that with small pulse widths (<1 µs), charge trapping occurs in the IL, whereas with longer pulse widths, it occurs in the FE layer. This result suggests a hierarchical distribution of charge trapping on different time scales. Ichihara et al.[34] identified two distinct forms of electron trapping through fast charge centroid analysis: read-induced e-trapping within interfacial SiO2 and program-induced e-trapping at the HfO2/SiO2 interface. Additionally, they reported that some of the electrons trapped at the HfO2/SiO2 interface were irrecoverable. Li et al.[47] discovered that the electron trapping/detrapping process occurs both in the Hf0.5Zr0.5O₂ (HZO) region and at the Si/SiO2 interface, which was determined by measuring the current transient corresponding to charge trapping/detrapping and extracting the exact time constant spectra.
From the standpoint of the energy level, Tasneem et al.[48] tracked the carrier capture and emission dynamics during write operations in n-FeFETs. Their findings revealed that electrons are trapped by acceptor traps with energy levels close to Ec, whereas holes are trapped by donor traps with energy levels close to Ev. The trapping occurs both within the SiO2 IL and at the SiO2/HfO2 interface. Zhao et al.[37] further elucidated the precise trap energy levels at the HZO/SiO2 interface through modeling of the relationship between the trapped charge and the fatigue process. This analysis revealed that one level is situated 0.36 eV above the conduction band minimum (CBM) of the Si substrate, whereas the other is located 0.76 eV below the valence band minimum (VBM).
Although the aforementioned studies provide an exhaustive analysis for understanding the charge trapping mechanism in FeFETs, they mainly focus on quasi-static conditions, which may not fully reflect the dynamic behavior in practical applications. Most of the analyses of charge trapping in the current literature are based on idealized experimental conditions, ignoring the effects of practical factors such as temperature variation and device aging on charge trapping. Therefore, future research needs not only to experimentally explore more diverse operating conditions, but also to develop more sophisticated models to predict and explain the kinetic behavior of charge trapping and its effect on the long-term performance of devices. Overall, the precise charge trapping/detrapping location may differ among different devices or test conditions, but it predominantly occurs in the IL, in the FE layer and at their interface, and the trap energy levels are close to the Ec and Ev of the Si substrate, which offers a general framework for optimizing the endurance of devices.
2.2 Asymmetric trapping/detrapping of electrons and holes
Owing to the differences in the nature of their charges, electrons and holes exhibit asymmetric behaviors during the trapping/detrapping process, which are manifested by different amounts of charge trapping and the ease of detrapping. The study of the asymmetric trapping/detrapping of electrons and holes is important for elucidating the respective roles of electrons and holes in FE fatigue.
2.2.1 Root causes
The asymmetric trapping/detrapping behavior of electrons and holes can be explained from three aspects. One aspect is the distinction between the energy band alignment during program and erase. Fig. 1 shows the energy band diagrams of Si FeFETs under a positive gate voltage with down-state polarization and under a negative gate voltage with up-state polarization. Compared with electron tunneling under the positive gate voltage, hole tunneling to the gate is impeded by the thicker barrier under the negative gate voltage, resulting in diminished hole injection. The second aspect is the discrepancy in the distribution of trap states near the conduction and valence bands. The third aspect is based on the assistance of polarization reversal in electron trapping.
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2.2.2 Asymmetric trapping
The most straightforward method for examining the asymmetric trapping of electrons and holes is to compare the numbers of trapped electrons and holes during the P/E process. Toprasertpong et al.[45, 49] conducted quasi-static split C−V and Hall measurements on n-type Si FeFETs and p-type Si FeFETs, respectively, to examine the electron/hole behavior under positive/negative gate voltages. By comparing the mobile inversion charge density Ns (obtained via Hall measurements) and the total charge density Ns + Nt (obtained via QS split C−V measurements) of the n-FeFET and the p-FeFET during the backscan process, it is found that the total electron density in the n-FeFET is approximately 1014 cm−2, whereas the mobile electron density Ns is only 1012 to 1013 cm−2, which is much lower than the total electron density, indicating that trapped electrons play a dominant role, and these trapped electrons are situated at the FE-HfO2/SiO2 interface. The slight discrepancy between the total hole density Ns + Nt and the mobile hole density Ns in p-FeFETs indicates that, in contrast to electrons, the majority of holes induced by each round of polarization switching are not trapped but are retained as mobile charges in the channel[45]. Figs. 2(a) and 2(b) show the schematic charge distributions in the n-FeFET and p-FeFET, respectively.
The extremely high trapped electron density at the FE-HfO2/IL interface originates from the electric field distribution when a positive gate voltage is applied. The voltage on the IL exceeds 30 MV/cm when the FE polarization is 10 μC/cm2, which is much higher than the typical breakdown electric field of SiO2 and facilitates electron injection from the Si substrate into the IL. When some electrons injected from the Si channel are trapped at the FE-HfO2/IL interface, they shield the electric flux from the FE polarization, which in turn decreases EIL. This process continues until the trapped electrons accumulate enough to maintain EIL below the critical electric field that induces electron injection.
Therefore, the electron trapping effect dominates the charge trapping phenomenon. Moreover, Shao et al.[16, 31] employed in situ threshold voltage measurements to demonstrate that severe electron trapping/detrapping may result in the formation of donor traps, which consequently results in diminished electron detrapping and augmented hole trapping. Ichihara et al.[34] found that partially trapped electrons become irrecoverable after cycling and trigger additional reversible hole trapping during erase. These findings suggest that electron trapping is not an isolated process; rather, it initiates a series of intricate changes in charge behavior, particularly an increase in hole trapping. The interplay between these two phenomena has a significant detrimental effect on device performance, thereby impacting its operational stability.
2.2.3 Asymmetric detrapping
Unlike electrons, once holes are trapped at the interface, detrapping becomes very difficult. The trapped electrons undergo continuous detrapping when the gate voltage varies from the maximum positive value to the reverse FE switching value, whereas the trapped holes cannot be detrapped when the gate voltage varies from the minimum negative value to 0 V[16, 31, 50]. As a result, the trapped electrons and holes exhibit asymmetric detrapping kinetics.
Although the density of holes trapped during one polarization switching cycle is very low and holes have a negligible effect on the polarization switching kinetics at the beginning of operation, the cumulative effect of these trapped holes has been demonstrated to become discernible after many cycles[48, 50]. This cumulative behavior indicates that trapped holes will impair the device performance after a certain number of operation cycles, and trapped holes have been proven to be more detrimental in terms of endurance degradation than electrons, even at a lower density[16, 31, 33, 34].
2.3 Nonlinear superposition of FE polarization and charge trapping
Charge trapping is inextricably linked to FE polarization. Previous research has indicated that charge trapping is barely detectable without FE switching and that the occurrence of charge trapping corresponds to the completion of FE switching[46]. FE polarization promotes charge injection from the channel into the FE layer by enhancing the electric field on the IL and changing the effective thickness of the tunneling barrier[44, 47]. However, the effects of FE polarization and charge trapping on the device performance (e.g., threshold voltage) are not linearly superimposed, and misuse of linear superposition may lead to significant underestimation of the charge trapping density in FeFETs[49, 51].
Toprasertpong et al.[49] investigated the joint impact of charge trapping and FE polarization by comparing the Q-EFE characteristics of a FeFET without electron trapping, a nonferroelectric MOSFET with electron trapping, and a FeFET with electron trapping. Here, Vth is defined as the Vg that induces a total charge in the Si substrate equal to the threshold charge density. Thus, regardless of whether FE polarization or charge trapping occurs at the FE/IL interface, the MW can be expressed as:
|
MW=V(1)th−V(2)th=(E(1)FEtFE+EILtIL+ψth+ϕms)−(E(2)FEtFE+EILtIL+ψth+ϕms)=(E(1)FE−E(2)FE)tFE. |
(1) |
Here, $ E_{\mathrm{FE}}^{(1)} $ and $E_\rm{FE}^{(2)}$ represent the electric field in the FE layer under two different polarization directions with a total charge density of ${Q} = {{q}}{{{N}}_0}$. In the FeFET without charge trapping, ${Q} = {{{P}}_{{\rm{FE}}}} + {\varepsilon _{{\rm{FE}}}}{\varepsilon _0}{{{E}}_{{\rm{FE}}}}$ is the charge density generated by the combination of the FE polarization and linear polarization at the gate capacitor, obtaining MW, as illustrated in Fig. 3(a). In the nonferroelectric MOSFET with electron trapping, ${Q} = {\varepsilon _{{\rm{FE}}}}{\varepsilon _0}{{{E}}_{{\rm{FE}}}}$. The total charge density at the gate capacitor (Vg = Vth) is ${Q} = {{q}}{{{N}}_0}$ without electron trapping and ${Q} = {{q}}({{{N}}_0} + {{{N}}_{{t}}})$ with electron trapping, resulting in a MW of $ \rm{M}\rm{W}_{\mathrm{trap}}=-qN_\mathrm{t}t_{\mathrm{FE}}/\varepsilon{_\mathrm{FE}}\varepsilon_0 $, as illustrated in Fig. 3(b). In the FeFET with electron trapping, assuming that there is only electron trapping with density Nt under down-state polarization and that the trapped electron density is much smaller than the polarization, $E_\rm{FE}^{(1)}$ is determined by the crossing point of the right side of the Q-EFE loop with ${Q} = {{q}}{{{N}}_0}$, whereas $E_\rm{FE}^{(2)}$ is determined by the crossing point of the left side of the Q-EFE loop with ${Q} = {{q}}({{{N}}_0} + {{{N}}_{{t}}})$, and the MW is illustrated in Fig. 3(c).
The comparison of the data in Figs. 3(b) and 3(c) reveals that the Vth shift induced by electron trapping in the FeFET is significantly smaller than that in the nonferroelectric MOSFET at the same trapped electron density, therefore:
|
ΔVbytrapinFeFETth≠qNttFE/εFEε0,MWFE+trap>MWFE+MWtrap>MWFE−qNttFE/εFEε0. |
(2) |
This result indicates that the effects of FE polarization and charge trapping on the threshold voltage are not linearly superimposed. Mistakenly assuming that $\Delta V_\rm{th}^{{\rm{by\;trap\;in\;FeFET}}} = q{N_\rm{t}}{t_\rm{FE}}/{\varepsilon _\rm{FE}}{\varepsilon _0}$ would lead to significant underestimation of the trapped electron density in FeFETs, which should be much worse in actual scenarios[33, 37, 52]. Subsequently, Toprasertpong et al.[51, 53] revalidated this viewpoint and conducted further investigations through device modeling, thereby resolving the expression of the MW in the presence of charge trapping as follows:
|
MW≈MW0−−NttFEεFEε0+ξ−tFEtanh(θ−−NtPs), |
(3) |
|
MW0≈{2PrtFEεFEε0,Pr≪εFEε0Ec2EctFE1+εFEε0EcPrtanh(η)η,Pr>εFEε0Ectanh(η)(2−1η), |
(4) |
|
θ±≈12[1∓√1−35εFEε0EcPsη], |
(5) |
|
tanh(η)=Pr/Ps. |
(6) |
Here Nt is the trapped charge density, and E± is the electric field in the FE layer at Vth,H (+) and Vth,L(−).
The appropriate relationship between Nt and ${{\Delta }}{{V}}_{{\rm{th}}}^{{\rm{by\;trap\;in\;FeFET}}}$ is derived from the charge‒electric field (Q‒E) relationship within the FE layer:
|
Nt≈ΔVth,trapCQSox+qNtεoxtFEe0, |
(7) |
where $C_{{\rm{ox}}}^{{\rm{QS}}} = \dfrac{\rm{d}{Q}}{\rm{d}{E}}$ is the capacitance corresponding to the slope of the hysteresis curve.
2.4 Impact of charge trapping on the device performance
On the basis of resolving the issues of the location, root causes, and characteristics of charge trapping/detrapping, we discuss the specific impacts of charge trapping, which include reduction of the MW and ION/IOFF ratio, degradation of the interface quality, and the read-after-write delay.
First, the parallel Vth shift resulting from charge trapping reduces the MW. As shown in Fig. 4(a), charge trapping shifts the threshold voltage, and the shift direction is opposite to that induced by FE switching. Zeng et al.[33] utilized the midgap voltage method to demonstrate that the midgap voltage shift is mainly contributed by charge trapping in the gate stack. They found that the amount of MW degradation is nearly equal to the difference of midgap voltage shift values between program and erase states. This finding further corroborates the hypothesis that charge trapping is the primary cause of MW degradation during FeFET fatigue. Notably, the majority of existing studies indicate that the diminished MW in n-FeFETs is attributable primarily to the presence of trapped holes in the gate stack[16, 31, 33, 34]. However, Zhao et al.[37] discovered that MW degradation is attributable to the increase in trapped electrons after the program operation rather than hole trapping/detrapping, which was determined by measuring the charges in both the metal gates and the silicon substrate. Consequently, further studies are necessary to elucidate the specific acting charge that causes MW reduction.
Second, the parallel Vth shift resulting from charge trapping reduces the ION/IOFF ratio. As illustrated in Fig. 4(a), electron trapping causes the threshold voltage to shift to the right, thus requiring a higher gate voltage to turn on the transistor, resulting in the transistor being unable to completely turn on at the originally set open-state voltage and a decrease in the open-state current. In contrast, hole trapping causes the threshold voltage to shift to the left, resulting in the transistor being unable to completely turn off at the originally set off-state voltage and an increase in the off-state current. As a result, the ION/IOFF ratio decreases[32].
Third, continuous back-and-forth tunneling of carriers during charge trapping/detrapping results in the deterioration of interface quality[28, 46]. As illustrated in Fig. 4(b), a substantial number of electrons are trapped during polarization switching with a positive Vg, and these electrons then combine with holes injected from the Si substrate when a negative Vg is applied for reverse polarization switching. The trapping of many electrons and subsequent recombination via hole injection during repetitive polarization switching cycles results in deterioration of the interfacial quality of HfO2-based FeFETs, which is accompanied by an increase in the leakage current and the formation of additional defects.
Ultimately, electron trapping results in read-after-write delay issue observed in transistors. In a n-FeFET, when the MW is measured immediately after programming with a positive gate voltage, the Vth offset is dominated by electron trapping and shows a rightward shift, and after the standby voltage is held for a period, this offset subsequently transforms into a FE-dominated leftward shift, as shown in Fig. 4(c). This phenomenon indicates that owing to electron trapping, the FE polarization state cannot be accurately read immediately after the write operation, leading to the read-after-write delay issue observed in transistors[46, 48, 49].
3. Fatigue mechanisms—trap generation
Charge trapping is based on the existing traps in the gate stack, and the generation of new traps typically occurs after charge trapping. Trap generation has been demonstrated to exert a more pronounced influence on endurance than initial traps[32, 54], which greatly affects the device performance. A comprehensive understanding of the mechanism underlying trap generation is essential for advancing our knowledge of the endurance degradation and enhancing the reliability of FeFETs.
3.1 Root causes and characterization methods
The causes of trap generation can be considered from two distinct perspectives: the energy released in electron trapping/detrapping and electron‒hole recombination and the interface damage induced by back-and-forth tunneling of electrons. Gong and Ma[32] investigated the evolution of Id‒Vg curves after alternating P/E cycles and discovered that during erase pulses, electrons tunnel through the IL and lose energy after entering the HfO2 region, with the lost energy being utilized to generate boundary traps near the interface, and that during program pulses, electrons tunnel via Fowler‒Nordheim (FN) or trap-assisted tunneling through HfO2 and lose energy after entering the Si interface, with the lost energy being utilized to generate interface traps. Jia et al.[30] investigated the behavior of electrons and holes during normal write operation (NWO) and floating body write operation (FBWO) via split I‒V measurements. They reported that the energy released from electron‒hole recombination can promote the generation of oxygen vacancy defects. Fig. 5(a) shows the kinetic behavior of electrons and holes during the NWO in a n-FeFET. When a negative gate voltage is applied, some of the trapped electrons gain sufficient energy to tunnel from the high-energy trap to the conduction band and subsequently flow out through the source/drain. Concurrently, holes from the bulk region are driven by the negative gate voltage to tunnel from the valence band to the donor trap energy level. Some of the electrons at the acceptor trap energy level recombine with the trapped holes, resulting in energy release and facilitating trap generation within the gate stack. The situation during the FBWO is shown in Fig. 5(b). The holes in the body region cannot be injected into the gate stack because of the floating body, which prevents recombination of the electrons and holes. In this case, the generation of traps is markedly diminished. Shao et al.[16] reported that severe electron trapping and detrapping, accompanied by back-and-forth tunneling of electrons, damages the interface, leading to the generation of donor traps, which was proven by in situ threshold voltage measurements. Additionally, Chai et al.[55] demonstrated, through the formation energies and charge transition levels (CTLs) of defects, that the oxygen vacancy defects are more favorable to form compared with other defects such as oxygen interstitial and Hf/Zr vacancy, which further elucidates the nature of the newly generated traps.
A variety of methods have been developed to investigate trap characteristics, including the low-frequency noise method[54, 56, 57], single-pulse charge-trapping methodology[28], fast charge centroid analysis[34], and the midgap voltage method[33]. Among these methods, the low-frequency noise method is a particularly efficacious approach for investigating charge traps in high-k dielectrics[58]. Since noise signals originate primarily from the trap states, interface defects, and oxide defects within a material, the low-frequency noise method can provide invaluable insight into the locations and energy levels of these defects, as well as their changes over time and with the external conditions. For example, flicker noise or 1/f noise can be employed to examine boundary traps in the gate dielectric situated close (1−2 nm) to the Si/SiO2 interface, whereas the generation‒recombination (GR) noise associated with the current fluctuations of individual charge carriers transferred between traps can be used to probe either individual defect centers generating random telegraphic signals (RTSs) in the gate stacks or individual defect energy levels within the depletion region of the transistor channel[56]. A nondestructive and comprehensive platform for analyzing FE gate stack traps can be constructed by combining the low-frequency noise method with conductance‒voltage (G‒V) and current‒voltage (I‒V) testing.
3.2 Trap generation position
During repeated P/E cycles, traps can be generated at any point within the gate stack, which has been studied by several research groups. In 2014, Yurchuk et al.[28] employed the single-pulse charge-trapping methodology and variable base level charge pumping technique to monitor the evolution of the trap density within the FE layer of FeFETs and reported that essentially no new bulk traps were generated within the FE layer during endurance testing, whereas the trap density in the IL increased by almost an order of magnitude. In 2018, Gong and Ma[32] reported that with ±6 V, 100 ns P/E pulses, the positive erase pulses result in charge trapping and subsequently cause a Vth shift after approximately 103 cycles, followed by boundary trap generation within the HfO2 region close to the IL after 106 cycles, as shown in Fig. 6(a); in contrast, the negative program pulse tends to generate interface traps at the IL/Si interface after 103 cycles, as shown in Fig. 6(b). This finding provides a basis for subsequent studies. In 2021, Ichihara et al.[34] demonstrated via fast charge centroid analysis that while the initial defects were predominantly concentrated at the HfO2/SiO2 interface, trap generation shifted to the IL during fatigue. This finding differs from that of Gong and Ma, suggesting that the location of the generated traps may change as the number of cycles increases. In 2022, Cai et al.[59] corroborated that traps may exist not only in the IL but also in the FE layer via the extended measure-stress-measure (eMSM) test. In the same year, Duan et al.[54] demonstrated via the low-frequency noise method that the trap density across the whole gate stack increases during cycling, which further substantiates the comprehensive perspective on the distribution of generated traps. In recent work, Tian et al.[60] further confirmed the generation of traps in the IL by examining the gate leakage currents and the expansion of the trap state density during cycling; however, no traps were generated at the FE/IL interface. This observation is consistent with the findings of Ichihara's research, collectively demonstrating the dynamic nature of trap generation locations.
Since current studies have identified the formation of traps in the FE layer, in the IL, and at their interface, the trap generation location may not be fixed but rather depend on the device materials, structure, fabrication process, etc. More in-depth studies are necessary to establish a comprehensive and systematic theoretical system.
3.3 Impact of trap generation on the device performance
As outlined in Subsection 3.2, traps can be generated at various positions within the gate stack; thus, the effects of these traps on the transistor performance should be related to their locations. Under a large electric field across the IL, the defects generated in the IL assist in carrier tunneling (TAT mechanism), resulting in a notable increase in the gate leakage current. This phenomenon can be easily observed through the variable base level charge pumping technique[28]. The enhanced leakage current further counteracts the FE polarization charge, ultimately reducing the MW[28, 54, 60]. The generation of FE/IL interface traps results in SS degradation, thereby reducing the MW and ION/IOFF ratio[32, 33], as illustrated in Fig. 7. It is noteworthy that both charge trapping and trap generation result in the MW reduction, with charge trapping being the primary cause of the MW reduction by inducing a threshold voltage shift. However, the MW reduction caused solely by charge trapping may recovered after detrapping. In contrast, once interface traps are generated, they cannot be reversed by electrical means, such as by applying detrapping pulses or increasing the delay time between write pulses. Trap generation at the IL/Si interface typically occurs after the application of a negative program pulse, under conditions different from those for trap generation at the FE/IL interface, this process also results in SS degradation[32]. Owing to the presence of FE polarization and the substantial electric field across the IL, the generation of traps in the FE layer has a negligible effect on the transistor performance[60].
From the perspective of the trap type, Shao et al.[16] found that the increased density of donor traps was essential for fatigue, which was demonstrated by in situ threshold voltage measurements. The donor trap generation reduces electron detrapping and enhances hole trapping, ultimately leading to the complete disappearance of the MW. Cai et al.[59] employed a standard eMSM sequence in FeFETs to identify two distinct types of traps based on the trapping dynamics and energy levels: the fast-type trap RA, located in the intermediate layer, and the slow-type trap RB, located in the HZO layer. These two types of traps were identified as the root causes of two significant reliability issues: the read-after-write delay and the MW degradation under bipolar pulse operation, respectively. In terms of the total number of traps, the number of RA traps initially increases within the first 103 cycles, followed by a period of stability from 103 to 104 cycles. In contrast, the number of RB traps continues to increase throughout the endurance test. In terms of trapping kinetics, as the number of cycles increases, the capture time and emission time of RA remain relatively constant. In contrast, the capture time of RB significantly increases while the emission time significantly decreases. This result suggests that trapping by RB becomes increasingly difficult. Additionally, in terms of the trap energy level, the energy level of RA remains constant after the capture of an electron, whereas the energy level of RB shifts to a much lower steady state after the trapping of an electron.
4. Optimization strategies of the fatigue effect
As previously stated, FeFET fatigue is caused by charge trapping and trap generation in the gate stack. Therefore, the most effective method for enhancing the FeFET endurance is to suppress trapping and passivate defects, which can be achieved by optimizing the operating conditions and the gate stack structure, as illustrated in Fig. 8.
4.1 Optimization of the operating conditions
First, the endurance of the device can be enhanced through electrical techniques: (1) appropriate detrapping sequences and delays[46, 61, 62], (2) fast I‒V reading during cycling[63] to reduce the Vth shift caused by charge trapping, (3) application of self-heating pulses between write cycles to partially redistribute and restore the traps[17, 36], and (4) reduction of the write voltage or time to achieve partial polarization switching[33, 52, 64, 65]. In addition to optimizing the electrical technology, Cai et al.[66] newly discovered the recovery of the MW in FeFETs under low-voltage operation, and an improved endurance can be attained through thickness scaling and fatigue recovery. Kirtania et al.[67] operated FeFETs at a cryogenic temperature of 77 K, achieving a 1.2x reduction in the write voltage, a 20x increase in the write speed, and unlimited cyclic endurance, validating the potential of cryogenic FeFETs as a last-level cache memory candidate for cryogenic high-performance computing (HPC) applications.
4.2 Optimization of the gate stack structure
The degradation of the interface quality and breakdown field of the IL represent crucial factors influencing charge trapping and trap generation, which can be addressed in three ways: enhancing the quality of the interface, thus reducing the initial trap density, suppressing trap generation, thus decreasing the probability of trapping, and eliminating the IL by using an oxide semiconductor channel.
4.2.1 Improve the interface quality
In terms of the fabrication methods, Oh[68] and Nguyen[69] applied high-pressure annealing to improve the quality of the IL and reduce the trap density at the FE/IL interface, the result of which was better under an atmosphere of 96% argon and 4% hydrogen, achieving an excellent endurance of 1010 cycles. Chen et al.[70] utilized low-temperature microwave annealing to reduce the leakage current and interface states. Zeng et al.[71] demonstrated a La-doped HZO-IGZO top-gate FeFET with a channel length scaled down to 40 nm without annealing, exhibiting a MW of 3.3 V, which is approximately twice as large as that without La doping. Concurrently, the device exhibits an endurance of up to 1010 cycles with a MW of 1.9 V, as well as 108 cycles with a MW of 3.1 V, which highlights the considerable potential of La-doped HZO for highly reliable FE memories for back end of line (BEOL) applications. Furthermore, the introduction of N elements into the SiO2 interlayer reduces the number of dangling bonds and other defects at the interface, thereby enhancing the passivation effect and effectively suppressing trap generation[18, 72−75].
In terms of the transistor structure, the insertion of IL is a commonly employed method, particularly for Al2O3 IL[76, 77]. For example, Lee et al.[78] employed in situ atomic layer deposition to introduce an ultrathin 2 nm Al2O3 IL between the HZO film and Si substrate, which effectively suppressed trap generation at the interface and increased the MW of the device. Hu et al.[79] inserted a 3 nm Al2O3 dielectric IL between the TiN gate metal and FE HZO, achieving a MW of 4.1 V with an endurance of approximately 104 cycles and a data retention time exceeding 10 years. In addition, Chai et al.[80] introduced a thin Al2O3 IL (~2 Å) between the HZO film and Si substrate, which suppressed oxygen vacancy generation in the gate stack, thus improving the MW of the device.
In terms of materials, Zhou et al.[23] simultaneously optimized the FE material and IL of FeFET. Compared with common HZO-based gate stacks, their innovative combination of Hf0.95Al0.05O2 and Al2O3 demonstrated enhanced endurance exceeding 5 × 109 cycles with a retention time of over 10 years. Peng et al.[81] prepared HfO2‒ZrO2 superlattice (SL) FeFETs with enhanced endurance, fatigue recovery, and data retention performance compared to HZO-controlled devices. After 1010 P/E cycles, the SL FeFET still achieved a MW above 500 mV with recovery. Shiokawa et al.[82] used thermally stable TiO2 as the channel material to prepare HZO-based FeFETs, which exhibited a high-speed, low-voltage P/E capability and excellent endurance for more than 1011 cycles while realizing full-channel switching.
4.2.2 Reduce the electric field across the IL
The electric field across the IL can be reduced in several ways: (1) High-k oxide can be used as interlayer or seed layer to reduce the electric field across the interlayer[19, 83−85]. The SiO2 interlayer is typically replaced by nitride film with larger dielectric constant, such as SiON, AlON, and Si3N4[18, 19, 73, 83, 86−89]. ZrO2 is frequently employed as a seed layer[84, 90−92] owing to its low crystallization temperature, which enhances the formation of the FE phase in HZO films. (2) The area ratio of the dielectric layer to the FE layer can be increased, including in Ω-gate FeFETs[93], FeFETs with notched channels (R-FeFETs)[94, 95], nanosheet (NS) gate-all-around (GAA) GexSi1−x FeFETs[24, 96, 97], and metal/ferroelectric/metal/insulator/semiconductor (MFMIS) structure with internal metal gates[98]. (3) The remanent polarization, spontaneous polarization and dielectric constant of the FE layer can be reduced[99−102] to diminish the charge mismatch between the FE polarization and the semiconductor charge. In addition, by employing an oxygen scavenging technique, Kim et al.[103] demonstrated improved switching voltage and endurance characteristics in n/p-type FeFETs based on HZO, which exhibited an excellent endurance of 1010 cycles.
4.2.3 Utilize oxide semiconductor channel
The most effective approach to solving the charge trapping and trap generation issue in FeFET gate stacks is to completely eliminate the IL; however, the chemical stability of SiO₂ makes this approach unachievable. The application of nonsilicon channel materials, particularly oxide semiconductor materials such as WOx[104], IGZO[105, 106], IGZTO[107], In2O3[108], and IWO[109, 110], enables the realization of FeFETs without interlayers, thereby offering a potential solution to this issue. In contrast to Si channel FeFETs, no IL is formed when the oxide semiconductor channel is in contact with FE-HfO2, thus achieving substantial enhancements in endurance[105−110] and improved read-after-write delay behavior[110]. Currently, a-IGZO is one of the most prominent oxide semiconductor materials owing to its high mobility, junction-free FET operation, nearly-zero low-k IL between channel and gate oxide, and effective capping for HZO FE phase formation[111−116].
5. Conclusions
In summary, both charge trapping and trap generation significantly contribute to fatigue of FeFETs, which can lead to various endurance issues, including MW degradation, ION/IOFF ratio reduction and the increase in the gate leakage current. The occurrence of charge trapping is based on the intrinsic traps within the FE layer, with asymmetric trapping and detrapping behavior of electrons and holes. Trap generation originates from the energy dissipation during charge trapping/detrapping and electron‒hole recombination, as well as interfacial damage. The traps generated at various locations may exert different effects on the performance of FeFETs. Consequently, the key to enhancing the endurance of FeFETs lies in suppressing trapping and passivating traps. We identify feasible optimization strategies and summarize the existing achievements in terms of optimizing the operating conditions and the gate stack structure, which are valuable references for future research. The main content of this paper and the connections between its various sections are summarized in Fig. 9. The poor endurance of HfO2-based FeFETs has been a severe obstacle to their development, and clarifying the mechanisms of FeFET fatigue and establishing targeted optimizations are crucial for realizing their application in not only novel nonvolatile memory technology but also neuromorphic computing, the IoT and logic-in-memory (LiM).
Acknowledgments
This work was supported in part by the National Natural Science Foundation of China (NSFC) under Grant 62304246, 62404246, 62425407; the Ministry of Science and Technology (MOST) of China under Grant 2022YFB3608400; the Young Elite Scientists Sponsorship Program by the China Association for Science and Technology (CAST) under Grant 2022QNRC001; and the Youth Innovation Promotion Association of Chinese Academy of Sciences under Grant 2020120, 2023127.
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