1. Introduction

The battery management system (BMS) is widely used in electric vehicles for managing and monitoring the voltage and current of the automotive battery arrays^[1]. The high-precision analog-to-digital converters (ADCs) used in BMS require an equally high-precision bandgap reference (BGR) to obtain more accurate battery voltage information. The voltage of lithium-ion cells usually ranges from 3.0 to 4.0 V, however, the voltage change from 10% to 90% state of charge is only 300 mV^[2]. Within this voltage range, to achieve a voltage measurement accuracy of 0.5% over the temperature range of −40 to 125 °C, the TC of the reference voltage of less than 3 ppm/°C is required. On the other hand, since most of the battery management integrated circuits (BMICs) are powered by battery arrays, the supply voltage to the BGR changes significantly during high-current charging and discharging, even with a DC−DC converter. As a result, for BMS applications, a BGR that maintains high accuracy under both temperature and supply voltage variations is required, as well as driving capability with continuous-time and adjustable outputs to meet the needs of other circuit modules in BMS.

In the conventional research on high-precision bandgap references, efforts have been made to eliminate the effects of op-amp’s offset and to compensate for the high-order nonlinear temperature dependence by various high order compensation techniques^[1−20]. The switched-capacitor based BGR can easily eliminate the offset of op-amp by using auto-zeroing as a part of the natural switching process^[2]. However, clock feedthrough and channel charge injection can still impair the reference voltage accuracy. On the other hand, chopping techniques can also be used to eliminate the influence of operational amplifier offset errors. In Ref. [3], the chopping technique was applied to a bandgap voltage reference circuit to achieve high precision. It achieves temperature coefficient (TC) ranges from 3.2 to 5.5 ppm/°C and average TC of 4.3 ppm/°C from −40 to 125 °C with only a narrow supply voltage range (1.8 V ± 10%)^[3]. Besides, the structure of BGR in Ref. [3] can only generate discrete-time reference voltages, making it suitable only for use in switched-capacitor based ADCs. Another high-order compensation method, known as the curvature correction technique, directly corrects the shape of a temperature curve without the need to identify the source of the error. The technique in Ref. [10] compensates for convex and concave curves using PTAT and CTAT currents from the BGR core. To enhance the effect, the method is to increase the number of correction currents. In Ref. [11], BGR uses six Nano-Ampere currents for curvature correction, achieving a suitable voltage by using a large resistor. However, the curvature correction current can be greatly affected by the chip-to-chip variation.

In addition to high-precision technology, the reference circuit used in BMS also requires an appropriate bandgap framework. The common BGR structures are divided into two types: voltage-mode and current-mode. The voltage-mode BGR is obtained by superimposing base-emitter voltage (V_BE) and ΔV_BE (where ΔV_BE = V_Tln(n), representing the base-emitter voltage difference between Q₁ and Q₂, and n is their emitter area ratio). This limits its output to approximately 1.2 V, making it hard to directly obtain a specified output voltage^[6−8]. Since the reference voltage (from 3.0 to 4.0 V) generation circuit for the battery management IC's analog-to-digital converter is composed of a bandgap reference and low-dropout regulator (LDO), the LDO provides gain to boost the bandgap reference output voltage to 3−4 V while driving the converter's input capacitance, with its loop bandwidth needing to satisfy the settling accuracy requirements during the sampling period. Elevating the bandgap reference output voltage enables reduction of the LDO's gain requirement, improvement of the loop feedback factor, relaxation of the amplifier bandwidth specifications, and consequent lowering of overall power consumption. Another solution is the current-mode BGR, which allows for easy adjustment of the desired output reference voltage by modifying the resistor value. The commonly used current-mode BGR core^[9] is shown in Fig. 1, which is capable of generating both the proportional-to-absolute-temperature (PTAT) current and the complementary-to-absolute-temperature (CTAT) current. As a result, adjusted-temperature-curvature correction currents can be generated to compensate for high-order nonlinearities due to the V_BE voltage, resulting in extremely small TC^[10]. The latest work achieves a minimum TC of 5.78 ppm/°C and an line sensitivity (LS) of 0.03%/V^[11], which cannot fully meet the requirements of BMS for a highly accurate reference voltage.

This work presents a high-precision bandgap reference circuit suitable for BMS applications, featuring an ultra-low TC, LS and designable output voltage. Adopting a current-mode topology enables precise 2.5 V reference generation, complying with the prevailing automotive-grade reference IC specifications (typically 2.5 V ± 5%) and optimally meeting BMS voltage reference requirements. Chopped op-amps are used to eliminate the dominate nonlinear offset. In order to address residual nonlinear errors without sacrificing power consumption, suitable curvature correction currents are designed to obtain ultra-low TC, averaging within 3 ppm/°C for low-cost two-point trimming and within 1 ppm/°C for multi-point trimming. In addition, the LS is optimized by the pre-regulation and can operate with a load of 1 mA.

The remainder of this paper is organized as follows. Section 2 provides a detailed analysis of error sources in BGR. Section 3 introduces the design techniques. Section 4 describes the overall structure of the proposed BGR. Section 5 presents the measurement results. Section 6 concludes the paper.

2. Error sources analysis

2.1 Analysis of dominant error sources

The errors in the conventional BGR are divided into linear errors and nonlinear errors. Linear error primarily refers to the variation error that is directly proportional to temperature and can be controlled through resistor trimming, whereas nonlinear error denotes errors that exhibit non-linear characteristics, which generally require error cancellation techniques or multi-point trimming to be optimized. A comprehensive analysis of the error contributions to the voltage-mode BGR was presented in Ref. [6], where the error sources are categorized into linear (accounting for 19%) and non-linear (accounting for 81%) as shown in Fig. 2. The linear errors include bipolar junction transistor (BJT) saturation current spread (8%), resistor spread (6%), and resistor mismatch (5%). All these linear errors that can be centrally corrected through trimming method. The middle pie chart is dominated by nonlinear errors, accounting for a substantial 81%. Dominant variations include significant contributions such as op-amp offset (78%), nonlinear temperature dependence of V_BE (2%), BJT current gain spread (0.6%), and BJT base resistance (0.4%). However, these errors cannot be easily corrected through trimming.

In this paper, we have adopted a current-mode bandgap reference voltage shown in Fig. 1. It utilizes a 5-branch current mirror, which additionally introduces an error source due to current mirror mismatch. This error includes both the linear and nonlinear parts, and also has a substantial impact. In the next Subsections, we will discuss the op-amp offset error, the nonlinear temperature dependence of V_BE errors in detail, which have dominant impact among the non-linear errors, while linear errors can be centrally corrected through trimming. Moreover, a comprehensive analysis of current mirror mismatch errors is presented in this Section.

2.2 Operational amplifiers input offset

In the current-mode bandgap core as shown in Fig. 1, the PTAT current and CTAT current are added to the resistor R_O through current mirrors to obtain the reference voltage:

$${V}_{\mathrm{R}\mathrm{E}\mathrm{F}}={R}_{\mathrm{O}}\left({I}_{\mathrm{P}\mathrm{T}\mathrm{A}\mathrm{T}}+{I}_{\mathrm{C}\mathrm{T}\mathrm{A}\mathrm{T}}\right),$$

(1)

$${V}_{\mathrm{R}\mathrm{E}\mathrm{F}}={R}_{\mathrm{O}}\left(\frac{{V}_{\mathrm{T}}\cdot \mathrm{ln}\left(n\right)}{{R}_{2}}+\frac{{V}_{\mathrm{B}\mathrm{E}1}}{{R}_{1}}\right),$$

(2)

where V_T = kT/q represents the thermal voltage, with k as the Boltzmann constant, and q as the electron charge. However, the offset of op-amps introduces additional errors. As shown in Fig. 3, assuming that the offsets of the two op-amps are V_OS1 and V_OS2, the expression for the reference voltage that includes the offset term is:

$${V}_{\mathrm{R}\mathrm{E}\mathrm{F}}'={V}_{\mathrm{R}\mathrm{E}\mathrm{F}}+{R}_{\mathrm{O}}\left(\frac{{V}_{\mathrm{O}\mathrm{S}1}}{{R}_{1}}+\frac{{V}_{\mathrm{O}\mathrm{S}2}}{{R}_{2}}\right).$$

(3)

Since the sum of CTAT current and PTAT current are close to zero at room temperature, and V_BE is much larger than ΔV_BE, R₁ is significantly larger than R₂. Due to the lower resistance value of R₂ compared to R_O, the V_OS2 will be multiplied by a factor much greater than V_OS1, significantly affecting the accuracy of the reference voltage.

2.3 Nonlinear temperature dependence of V_BE

The voltage accuracy of bandgap references suffers from another high-order nonlinear temperature dependence from the V_BE voltage, so first-order temperature compensation is far from sufficient to obtain a reference voltage with an ultra-low TC. According to Ref. [12], there exists a quantitative relationship between V_BE and temperature (T):

$${V}_{\mathrm{B}\mathrm{E}}={V}_{\mathrm{g}00}-\lambda T+c\left(T\right),$$

(4)

$${V}_{\mathrm{g}00}={V}_{\mathrm{g}0}+\left(\eta -m\right)\frac{k{T}_{\mathrm{r}}}{q},$$

(5)

$$c\left(T\right)=\left(\eta -m\right)\frac{k}{q}\cdot \left(T-{T}_{\mathrm{r}}-T\mathrm{l}\mathrm{n}\frac{T}{{T}_{\mathrm{r}}}\right),$$

(6)

where the V_g0 is extrapolated bandgap voltage at 0 K, the empirical approximate value is 1.156 V, η is a constant which is slightly related to the doping level. For the coefficient m, there is I_C ~ T^m. In this structure, I_C is a PTAT current which is generated by ΔV_BE, therefore m = 1.

In Eq. (4), −λT is the first-order term and c(T) is the higher-order nonlinear term. The term c(T) has the largest effect on the TC after superimposing the ΔV_BE voltage for first-order compensation. Since the graph of c(T) is a convex curve, the reference voltage also exhibits a convex curve shape without the influence of other factors and has a zero TC at T_r.

2.4 Current mirror errors

To evaluate the proportion of linear and nonlinear effects of current mirrors under this 0.18 µm process technology, we performed Monte Carlo simulations. As shown in Fig. 4, 10 Monte Carlo simulation results demonstrate that after first-order temperature compensation adjustment through R₀ and R₁, along with trimming to 2.5 V output voltage, all first-order temperature compensation curves converge as illustrated in Fig. 4(b). The nonlinear dispersion ranges from 560 to 615 μV, which represents a relatively small percentage of the 2.5 V output voltage. For current mirror mismatch, we primarily adopted a linear error compensation approach through trimming. The impact of current mirror mismatch on the curvature of the reference voltage is minimal and can be almost eliminated through resistor trimming (R₁, R₀).

3. Design technique

The process affects the error evaluation results. For example, under different process conditions, the spread of the base doping and spread of transistor dimension of the BJT transistor, the spread and mismatch of resistors, and the influence of process on the saturation current gain of the BJT transistor all have an impact. Additionally, the base parasitic resistance of the BJT transistor is affected to varying degrees under different processes. For different fabrication processes, it is necessary to re-evaluate the error proportions. The 0.16 µm process used in Ref. [6] provides a general benchmark. This design employs a 0.18 µm process, and a detailed simulation-based error assessment was conducted after finalizing the bandgap reference architecture.

The selection of the operational amplifier (op-amp) also have a certain impact on the evaluation. To achieve high precision, a low-offset op-amp is employed in the design. A folded cascode structure is utilized, and based on the theoretical analysis of the op-amp's offset voltage, the input pair is designed with a larger W/L ratio to obtain higher transconductance, while the current mirror adopts a smaller W/L ratio for lower transconductance. Additionally, larger dimensions are used wherever possible to minimize mismatch (1 µm/20 µm for current mirrors and 8 µm/4 µm for input transistor pair). As a result, the input offset voltage of the op-amp is approximately 921 µV.

When selecting the type of resistor, the change in resistance value with temperature should be considered first. In the 0.18 µm process library, there are various types of resistors. Generally speaking, poly resistors have relatively low parasitic capacitance and leakage. We set each type of resistor to a value of 100 kΩ and then simulated the relationship between resistance and temperature, obtaining the simulation results shown in Fig. 5. From the simulation results, the rpposab resistor has the smallest temperature coefficient. Therefore, in the circuit design, we have selected rpposab as the resistor of choice for this 0.18 µm process.

In this work, to emphasize the most critical error factors among various error sources, the simulated error proportions listed in Table 1 represent the contribution of each error source to the total variation relative to the combined variation induced by all errors. The dominant errors are shown in Table 1, the op-amp offset is 82.4%, the current mirror mismatch is 7.7%, the BJT variation is 7.3%, and the process variation and mismatch of the resistors contribute 2.6%. Among them, op-amp offset and variation of the BJT process variation contribute to nonlinear errors, while process variation and mismatch of the resistors contribute to linear errors. Mismatch of the current mirror includes both nonlinear and linear errors.

As evidenced by the distribution in Fig. 2, we have adopted distinct compensation strategies for different error types: linear errors are systematically addressed through trimming techniques, while for nonlinear errors, we focus on compensating the dominant 78% contribution from op-amp offset. The remaining nonlinear errors, regardless of their origins, are collectively corrected through curvature compensation to achieve higher-order temperature curve shaping.

To reduce circuit power consumption, the chopping technology is chosen in this work. For the remaining mismatch nonlinearity and the smaller proportion of nonlinear errors, we employ curvature correction technology to deal with together. In the following subsections, we will introduce the chopping technique and curvature correction technique, respectively. The trimming method will be discussed in Section 4, together with the measurement discussion.

3.1 Chopping technique

The use of chopper modulation technology can alleviate the negative impact of amplifier input offset voltage V_OS and noise on the bandgap reference. During the chopper modulation process, the low-frequency input signal undergoes chopping modulation at the input of the op-amp, being modulated onto the chopping frequency. The chopping signal is a square wave with a frequency of f_ch. The chopping frequency is generally much higher than the frequency of flicker noise. After chopping modulation, the input signal is multiplied by the chopping signal and converted to the odd harmonic frequencies of the chopping signal. Then, upon reaching the op-amp input, the modulated signal is added to the op-amp's offset voltage and flicker noise, and the resulting mixed signal is amplified by the op-amp. The second chopper modulator at the op-amp output will modulate the amplified signal. At this point, the high-frequency useful signal is modulated back to the signal frequency, while the low-frequency offset and flicker noise are modulated to high-frequency. Finally, the demodulated signal is passed through a low-pass filter to remove high-frequency noise and offset, outputting a useful signal that is almost free of noise and offset. The specific circuit implementation is shown in Fig. 6. The modulator is placed at the input terminal and the demodulator the folding nodes.

We chose to use a PMOS-input low-voltage folded cascode operational amplifier primarily for the following two reasons: First, the input voltage of the operational amplifier is the V_BE voltage of the BJT transistor, which ranges approximately between 500−700 mV, and the PMOS-input folded cascode structure is well-suited to meet this voltage requirement. Second, this structure can provide high gain, ensuring that the circuit's performance meets the desired objectives.

For chopper technique utilized in the PMOS-input folded cascode operational amplifier, the V_BE voltage signal is inherently near-DC, implying that the signal frequency is low. As a result, the bandwidth requirements for the op-amp are not high. Thus, the primary constraint is low-frequency noise (such as 1/f noise), that the frequency cannot be too low. Another constraint is related to filtering. The higher the chopping frequency, the higher the frequency at which the V_os and low-frequency noise are modulated. With the same filter structure, higher chopping frequency makes filtering easier and improves the filtering effect. However, a higher chopping frequency also increases power consumption. In this case, a trade-off between these factors needs to be considered. In this design, the chopped operational amplifier utilized to address offset issues, was designed taking into account the mentioned trade-offs, and a clock frequency of 20 kHz is chosen for the operational amplifier. As illustrated in Fig. 7, through 1000 Monte Carlo analyses, it is evident that the global sigma of the offset error before employing the chopper was 18.13 mV. After implementing the chopper technique, the global sigma of the error was reduced to 103.5 µV.

3.2 Curvature correction technique

After using chopping technique to address the op-amp offset, nonlinearity temperature dependence of the V_BE becomes the dominant factor in nonlinear errors, resulting in a parabolic shape for the first-order compensated temperature curve. Consequently, this design incorporates a segmented curvature compensation technique to address this limitation. This work converted to a correction voltage using a smaller resistor, which, combined with two-point trimming.

Fig. 8 shows the structure of this curvature compensation circuit, which generates compensation currents ( I_COMP = I_CH + I_CL ) for the high temperature range (T_H) and low-temperature range (T_L)^[11]. These compensation currents are injected into the resistor (R_C) of the output branch to achieve curvature compensation for the output voltage. The compensated bandgap output voltage can be expressed as follows:

$${V}_{\mathrm{R}\mathrm{E}\mathrm{F}}={(I}_{\mathrm{P}\mathrm{T}\mathrm{A}\mathrm{T}}+{I}_{\mathrm{C}\mathrm{T}\mathrm{A}\mathrm{T}})\left({R}_{\mathrm{O}}+{R}_{\mathrm{C}}\right)+{I}_{\mathrm{C}\mathrm{O}\mathrm{M}\mathrm{P}}{R}_{\mathrm{C}},$$

(7)

where (I_PTAT + I_CTAT)(R_O + R_C) is the output voltage of first-order compensation, and I_COMPR_C is the voltage for curvature compensation. The principle of the curvature compensation technique which relies on the first-order compensated curve is shown in Fig. 9. When the vertex of the first-order compensated curve shifts horizontally relative to V_OPT (the nominal curve), there will be under-compensation or over-compensation at T_L and T_H. Additionally, although vertex does not shift, variations in curvature magnitude can also lead to under-compensation or over-compensation. Due to process variations and mismatches, the first-order compensated curves of different chips deviate from the V_OPT to varying degrees. Thus, it is necessary to employ trimming techniques to align the first-order temperature curves of different chips. This design uses two-point trimming at 20 and 60 °C to achieve close vertex positions for the first-order compensated curves across chips. Since the offset voltage V_OS2 of op-amp A₂, when translated to the output, is multiplied by a significant factor R₀/R₂ and varies with temperature^[11], it can lead to varying degrees of random changes in the magnitude of the curvature of the first-order compensated curve after two-point trimming. These offset issues have been mitigated using chopping technique in Subsection 3.1 and variations in curvature magnitude can be suppressed using trimming method, thereby reducing the random offsets value of the curvature of the first-order compensated curve.

In Fig. 10, the simulation results show that the parabolic temperature curve after first-order compensation still has a voltage error of 8.18 mV between −40 and 125 °C, which can be reduced to 372 µV through curvature correction. The test results show that the parabolic temperature curve after first-order compensation still has a voltage error of 6.5 mV between −40 and 125 °C, which can be reduced to 405 µV through curvature correction. Therefore, curvature correction can effectively perform high-order error trimming control.

4. The proposed BGR

4.1 Circuit design

Fig. 11 shows the overall structure of the proposed BGR. This structure encompasses several crucial components, including the chopped folded-cascode op-amp setup, two LDOs, a curvature compensation circuit, as well as associated clock generators and current sources. CLK_EN serves as the startup enable signal for both the clock generation circuit and the bandgap reference circuit. When CLK_EN is at V_DD, the gate voltage V_G of M₆ is pulled low, causing V_DDX to approach the supply voltage and initiating the bandgap reference core module, with V_REF1 reaching approximately 2.5 V. When CLK_EN is at 0, the clock generation circuit begins outputting a clock signal of around 20 kHz, activating the pre-regulation module. At this stage, V_DDX stabilizes at about 3.8 V to power the bandgap reference core, completing the circuit startup sequence.

The chopped folded-cascode op-amp configuration operates based on a 20 kHz signal provided by the clock generator. In addition to supplying the clock signal to the op-amp, this clock generator also furnishes 500 nA currents to both the op-amp and itself, ensuring their proper functioning. On the other hand, the compensation circuit plays a significant role in the BGR, employing curvature correction currents in the range of a few hundred nano-amperes to enhance circuit performance. During multi-point trimming, a total of six curvature correction currents are utilized to achieve more precise correction effects. Additionally, four out of the six curvature correction currents are employed during two-point trimming with fixed curvature correction code.

Although the chopping technique effectively eliminates the offset of the operational amplifier, directly using the output of the current-mode BGR core as the reference voltage leads to a significant ripple in the output voltage. This large ripple fails to meet the voltage stability requirements of components in the BMS other than ADCs, such as LDOs and temperature sensors. Although passive filters can be used to reduce the output voltage ripple to a low level, the use of passive filters significantly weakens the driving capability of the BGR. This is an unfavorable factor for circuits that need to provide sufficient power to the load. Whether obtaining the clock signal required for the chopper from an external input or integrating a clock generator within the circuit, there are a series of issues. Furthermore, the area occupied by the clock generator needs to be considered, and the circuit layout must be carefully planned to prevent the oscillating clock source from causing severe interference to the reference voltage.

To address these issues, a series of targeted actions have been implemented. A passive RC low-pass filter (LPF) is employed after the chopped op-amps on chip. Through its filtering effect, a stable and low-ripple voltage output can be obtained, improving the voltage quality. Simultaneously, the addition of an output LDO enhances the driving strength of the BGR, enabling it to provide a maximum of 1 mA current to the load, meeting the power requirements of the load. This LDO is powered from a 5 V supply and has an output voltage of 4 V, so the bandgap core is unaffected by changes in supply voltage from 4 to 5 V. Since the LDO also needs a reference voltage, the output of the BGR core is used as the reference and a start-up circuit is designed to ensure proper operation of the circuit. When the circuit is powered up using 5 V, the BGR core will first be supplied with 5 V as well, waiting for it to start-up and for the LDO to stabilize the 4 V output. Then, the power supply of the BGR core is switched to the LDO’s output to achieve independence from the external power supply. Two LDOs are utilized in the BGR. One LDO is primarily responsible for maintaining the stability of the core's output voltage, while the other LDO performs pre-regulation through a 3 : 5 resistance ratio.

5. Measurement results

The proposed BGR was fabricated using a 180 nm CMOS process with a total area of 0.548 mm². The chip micrograph is shown in Fig. 12. It consumes 84 μA at 25 °C with an LS of 42 ppm/V from 4 to 5 V, as shown in Fig. 13(a). We conducted simulation evaluations of 100 Monte Carlo runs to analyze the temperature-dependent characteristics of the error amplifier (EA). As shown in Fig. 13(b), the curve exhibiting the maximum offset deviation was identical to that displaying the greatest temperature-induced variation range. The maximum offset of 3.72 mV occurred at −40 °C. Since the output voltage is 2.5 V, this offset has relatively minor impact on the overall performance. The temperature coefficient was ultimately evaluated based on test results measured at the LDO output terminal.

5.1 Trimming methods

For the measurement trimming approach of chips, we can use curvature correction in conjunction with lower-cost two-point trimming at 20 and 60 °C near room temperature, as well as higher-precision multi-point trimming. The two points in two-point trimming are reflected in the alignment of the first-order parabolic temperature curve at 20 and 60 °C as shown in Fig. 14. The temperature range of our circuit is from −40 to 125 °C, and the midpoint of this temperature range is 40 °C. To ensure the accuracy of trimming and reducing the trimming cost (near room temperature trimming), we first perform trimming at 20 and 60 °C. The mean temperature coefficient at this stage is measured at 15.9 ppm/°C for 38 chips. The subsequent curvature correction uses the same trimming code and does not require chip-to-chip adjustments. In contrast, multi-point trimming refers to the process where, after aligning the first-order parabolic curve at the two points (20 and 60 °C), the temperature range from −40 to 125 °C (outside of 20 and 60 °C) is divided into intervals of 15 °C for compensation. The curvature correction current slope is adjusted at each interval, and this requires chip-to-chip trimming. After the temperature trimming is completed, it is only necessary to adjust the voltage to 2.5 V at room temperature to complete all trimmings.

Two-point trimming of the BGR, involves adjusting resistors R₁ and R_O. R₁ modifies the CTAT current of the BGR core, while R_O adjusts the reference voltage. Fig. 15 depicts this process, where voltages at 20 and 60 °C are matched for each R₁ code to achieve symmetry around 40 °C. The automatic test equipment (ATE) completes this in seconds. Once the optimal R₁ code is determined, curvature correction currents will be engaged to refine the TC. The process concludes with R_O adjustment to yield a 2.5 V reference voltage. It should be noted that, modifying R₁ inversely affect the curvature-correcting I_CTAT current, consequently influencing the trigger temperatures (T_L and T_H). While this impacts the fixed-code correction effectiveness in the 20 °C/60 °C two-point trimming alignment, the effect is less pronounced in the 15 °C-step chip-to-chip multi-point trimming approach.

Fig. 16 illustrates the schematic of two-point trimming of the proposed bandgap voltage reference using ATE. On-chip IIC circuitry for unified control of all trim switches. With ATE, two-point trimming can be programmed for fast automated trimming without human intervention.

To achieve superior TC, multi-point trimming adjusts curvature correction currents. Select 4−5 temperature points from −40 to 125 °C and fine-tune each correction current to achieve under 1 ppm/°C TC across the range.

5.2 Test results

Fig. 17 illustrates the test results using two-point trimming with fixed curvature correction code for 38 chips. The average output voltage is 2.5004 V. The trimmed TC ranges from 0.89 to 5.88 ppm/°C, with an average TC of 2.69 ppm/°C and a sigma of 1.34 ppm/°C. In addition, the test results of multi-point trimming are also available for 20 chips, as shown in the Fig. 18. The multi-point trimmed TC ranges from 0.64 to 0.98 ppm/°C, with an average TC of 0.81 ppm/°C. Fig. 19 presents the measured noise spectrum and PSRR of V_REF at room temperature. The measured integrated noise from 0.1 to 10 Hz is approximately 16.2 μV_RMS. The measured PSRR is −70.2 dB at 10 Hz. The static power consumption without the output load is 84 µA. The maximum output load current is 1 mA. The chip's transient characteristics are shown in Fig. 20, demonstrating a startup time below 3 ms and output ripple within 300 µV.

Table 2 summarizes the performance of the proposed BGR and compares it with state-of-the-art high-precision BGRs. The measured average TC of 2.69 ppm/°C achieved through two-point trimming is the lowest reported compared to other works without multi-point trimming at currents below 200 μA. Although Ref. [14] has a smaller TC, the temperature range is −25 to 125 °C and the power consumption is larger. The proposed BGR has a driving capability of 1 mA and an LS second only to Ref. [14], while consuming less power and a designable output voltage. On the other hand, while the multi-point trimming approach in Ref. [20] achieves a comparable mean temperature coefficient (2.4 ppm/°C vs. 2.69 ppm/°C), its output lacks current-driving capability. In contrast, our measured results incorporate the error contribution from the LDO buffer's error amplifier while delivering 1000 μA load current, yet still maintain the same precision level below 3 ppm/°C. The extensive testing on 38 chips provides a robust validation of the proposed BGR's performance, making it more convincing.

6. Conclusion

This paper presents a high-precision BGR with an ultra-low TC, LS and designable reference voltage for high accuracy BMS applications. In order to eliminate the offset of op-amps, chopped op-amps are employed. A LDO is employed to enable the BGR to deliver a maximum load current of 1 mA, while a pre-regulator circuit is used to improve its LS. Finally, curvature compensation technique is combined with two-point trimming and multi-point trimming, respectively, to achieve ultra-low TC for each chip. The BGR was fabricated using a 180 nm CMOS process, with an active area of 0.548 mm², a current consumption of 84 μA at a 5 V supply voltage, and an LS of 42 ppm/V. Tests on 38 chips have shown an average output voltage of 2.5 V, an average TC of 2.69 ppm/°C after two-point trimming and 0.81 ppm/°C after multi-point trimming. These results indicate that this BGR can provide an ultra-low TC, LS and designable reference voltage for BMS systems.

Acknowledgments

This work was supported by the National Natural Science Foundation of China (NSFC) under grant No. 62204235.