Xinyu Jiang received the B.S. degree from Harbin Institute of Technology, Harbin, China, in 2022. She is currently pursuing the M.S. degree in Tsinghua University. Her research interests include mm-wave integrated circuits, phased array systems and wireless transceiver design.
Wei Deng received the B.S. and M.S. degrees from the University of Electronic Science and Technology of China, China, and the Ph.D. degree from Tokyo Institute of Technology, Japan. Currently, he is with the Tsinghua University as an Associate Professor. Dr. Deng is a TPC Member of ISSCC, VLSI, RFIC, CICC, A-SSCC and ESSCIRC. He has been an Associate Editor and a Guest Editor of the SSCL, a Guest Editor of JSSC, and a Distinguished Lecturer of the IEEE SSCS. His research interests include RF, mm-wave, terahertz, and mixed-signal integrated circuits and systems for wireless communications and radars.1. Introduction
The 5G NR has defined FR2 n257 (26.5−29.5 GHz) and FR2 n258 (24.25−27.5 GHz) for wireless communication in millimeter-wave bands, which promises sufficient spectrum resources in contrast with FR1. To meet the high data rate throughput in 5G FR2 band, mm-wave communication systems typically employ high-order modulation schemes, such as 16-QAM, 64-QAM, and 256-QAM modulated signals. However, those signals are with high peak-to-average power ratio (PAPR), requiring an excellent linear and PBO efficiency performance of the transmitting system. For instance, PAPRs of 16-QAM and 64-QAM SC signals are in the range of 6 to 7 dB and PAPRs of 16-QAM and 64-QAM OFDM signals are in the range of 10 to 11 dB[1]. As the output module of the transmitting system, the PA determines the overall performance in terms of linearity and efficiency to a large extent. To meet the strict EVM requirement and to minimize the power consumption when PA works at the average power status, several kinds of efficiency enhancement techniques for linear PAs have been proposed[2]. A conventional outphasing power amplifier divides a non-constant envelope signal into two constant envelope signals at input and sums them in vector at output, achieving an excellent amplitude modulation of two phase-modulated (PM) signals[3, 4]. To generate two PM signals for accurate linear output, an extra wideband digital modulator is needed and thus increases the difficulty of circuit design and integration. The working principle of envelop-tracking (ET) power amplifier can be explained as a similar envelope-derived modulation to the supply voltage of a traditional linear power amplifier[5, 6]. However, a high-speed supply modulator is often difficult to design, causing the misalignment of amplitude information and phase information under the wideband modulated signal. When it comes to load modulated balanced amplifier (LMBA)[7, 8], an auxiliary PA is used to replace the 50-resistor load at the isolation port of the output quadrature coupler compared to the traditional balanced amplifier (BA). The load impedance of LMBA can be effectively modulated through the appropriate amplitude and phase of the auxiliary PA. However, the additional control-signal path consumes extra chip area, which is undesired for system-level integration.
Compared with those linear PA mentioned above, Doherty PA brings a direct and easy power back-off (PBO) linear and efficiency enhancement solution in RF front-end. The working principle of Doherty PA is called active load-pulling, in which the load resistance of one way is changed when the current of another way is changed adaptively in response to the input signal. In order to decrease impedances seen by the output of main and auxiliary paths gradually from PBO to the saturation state, a quarter-wave transmission line (QTL) is needed for impedance inversion, either at the output of main path in parallel-Doherty PA (PDPA) or at the output of auxiliary path in series-Doherty PA (SDPA). However, existing Doherty PAs suffer from large silicon area due to traditional QTL[9], and the limited operating frequency range due to the inherent narrowband of conventional impedance inverting network (IIN)[10]. In order to overcome the above-mentioned issue, this work introduces a SDPA with distributed multi-step IIN, which acts as a wideband QTL and power combiner.
Fabricated in a 65 nm CMOS technology, the proposed SDPA achieves a 3 dB bandwidth from 21.5 to 37 GHz. Its maximum measured Psat is 17.5 dBm and the maximum measured OP1dB is 14.7 dBm. Besides, the maximum measured peak, OP1dB, and 6dBPBO PAE results are 28.2%, 23.2%, and 13.2%, respectively. Across 21 to 30 GHz, the measured Psat and OP1dB are over 16 and 13.4 dBm. In the same condition, its measured peak, OP1dB, and 6dBPBO PAE results are above 20.4%, 16.2%, and 9%. Without DPD and equalization, the proposed SDPA achieves −33.35, −23.52, and −20 dB EVMs for 100 MHz 256-QAM, 600 MHz 64-QAM, and 2 GHz 16-QAM signals at 27 GHz. Besides, EVMs are lower than −25.2 dB for 200 MHz 64-QAM signals between 22 and 31 GHz without DPD and equalization.
This article is organized as follows. The design principle of broadband series-Doherty power combiner is first introduced in Section 2, including the theory of efficiency enhancement of two-way Doherty PA and the analysis of typical power combiners and bandwidth of IIN. The topology of proposed SDPA, including the implementation of the proposed series power combiner and other design details of this work, are discussed in Section 3. Then, the results under continuous-wave (CW) and modulation measurements of the proposed SDPA are shown in Section 4. Finally, the comparison and conclusion are given in Section 5.
2. Design principle of broadband series-Doherty power combiner
2.1 Theory of efficiency enhancement of two-way Doherty PA
Linear PA is biased over their threshold point and its drain current can be swung up to the maximum linear value, Imax, at saturation. Take an ideal class-B PA, whose transistor is biased at its threshold point and knee voltage is ignored, for an example. Its value of load resistor Rload, RF output power, and drain efficiency at saturated status under power supply Vdc can be figured out to be 2Vdc/Imax, Vdc∙Imax/4, and π/4, respectively[11].
In order to fit the situation of PBO, the voltage amplitude of the input signal is supposed to be reduced by a factor n from saturation mentioned above. When the transconductance of transistor is assumed perfectly linear, the peak value of drain RF current is reduced by the factor n, making its fundamental component also reduced by the same factor. As the load resistor stayed the same as Rload, the fundamental component of drain RF voltage is shrunk by the factor n as well. As a consequence, drain efficiency is π/4n and dropped by the factor n from saturation, which means more power consumption to achieve high linear output power in this condition.
Active load modulation is introduced in the design of two-way Doherty PA. When output power is smaller than 1/n2 of which in saturated status, only main path works as a linear PA. By designing its load resistor as n∙ Rload, the output voltage can be swung to maximum at 1/n2 PBO status, reaching the same peak drain efficiency as at saturation. As the input signal becomes lager, the auxiliary path gradually turns on, whose bias changing from class-C level to class-B level. The effective value of load resistance, at the same time, adaptively decreases due to the active load-pulling from the auxiliary path. This ingenious operation makes the voltage swing of main path maintain in the same constant maximum condition as the status of 1/n2 PBO while the drain current continuing increases. As a consequence, the overall drain efficiency is held at a high level throughout the period from 1/n2 PBO to saturated status.
In theory, when the proportion of main path’s current Imain to peak point of drain auxiliary path’s current Iaux at saturation is set to k, the efficiency at PBO status can be designed accordingly, achieving different ranges of efficiency enhancement. Take T-line based two-way PDPA, as shown in Fig. 1(a), for an example. Its drain efficiency performance is shown in Fig. 1(b), indicating a deeper PBO status of the first peak efficiency when the proportion k is becoming smaller.
However, the deeper PBO level first peak point reaching, the deeper is the depression of the efficiency curve from PBO to saturation. Meanwhile, the larger impedance transformation ratio (ITR) in deep PBO status is needed for IIN as shown in Fig. 1(c), causing limited bandwidth and difficult layout implementation. Therefore, equal current distribution is often employed in the practical design. In this case, the auxiliary path generates an output power proportional to the cube of the increasing input voltage amplitude and the main path generates an output power proportional to the square root of the increasing input voltage amplitude, achieving an excellent composite linear characteristics of output power and high-level efficiency during the period from saturation down to 6 dB PBO status.
2.2 Analysis of typical two-way Doherty power combiners
As shown in Fig. 2, typical methods of two-way power combining include series power combiner and parallel power combiner, first of which synthesizes power by voltage mode and second of which sums power by current mode[12]. When matching networks are based on transformers, the output impedance of each path is supposed to be converted from Zopt_ser to RL/2 in two-way series combiner and from Zopt_par to 2RL in two-way parallel combiner. Simplified models of transformer have been proposed in published articles[13−15], in which the relationship between the bandwidth performance of impedance matching and the coupling coefficient k between two resonators has already been discussed in detail. In a nutshell, a broadband matching network can be realized only when the k factor is large enough, which further requires similar real part of source impedance Ropt and either load impedance RL/2 in series combining method or 2RL in parallel combining method for practical layout implementation.
Under CMOS process, pseudo-differential common-source (CS) amplifier with capacitor neutralization, as shown in Fig. 3(a), is typically used for its better breakdown resistance and efficiency performance compared with multiple transistors stacked structures. And its small signal equivalent circuit is shown in Fig. 3(b)[16], where CL is the load parasitic capacitance, and R is the parallel equivalent load resistance including the transistor output impedance and the loss of inductor L. How to eliminate the Miller effect brought about by Cgd can first be discussed. To be specific, the feedback from drain to gate via Cgd and CC are respectively given by
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vgsVout(s)|Cgd=sCgd[rg(1+srsCC)+rs]s(Cgs+Cgd)[rg(1+srsCC)+rs]+srsCC+1, |
(1) |
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vgsVout(s)|Cc=−srsCCs(Cgs+Cgd)[rg(1+srsCC)+rs]+srsCC+1. |
(2) |
Note that those two kinds of feedback can cancel each other when the sum of Eqs. (1) and (2) is zero. In this case, CC is figured to be
|
CC=Cgd(1+rgrs). |
(3) |
As the gate resistance rg is typically small, neutralizing capacitor Cc can be directly designed the same as Cgd to achieve excellent isolation between input and output, through which the stability and gain of PA are improved.
When simply considering a n-multipliers m-fingers transistor as many small transistor units combining in parallel at device level, there comes to a conclusion that a bigger W/L transistor is required in order to meet higher saturation output power for common-source structure since Imax becomes larger at the same time. The simulated relationship between the size of transistors in actual differential CS amplifier with 32 fingers under 65 nm COMS and two parts of Zopt, Ropt and Copt (note that Z∗opt = Ropt || Copt), is plotted in Fig. 3(c), indicating a lower Ropt with the number of multipliers increasing. According to the impedance matching characteristics mentioned above, two-way series power combiner is more suitable for high saturation power and broadband performance as each path’s load impedance is a quarter of two-way parallel power combiner.
After the concept of active load-pulling operation is introduced, how impedances change from 6 dB PBO to saturation can be further discussed. As shown in Fig. 4(a), impedances seen by the output in main and auxiliary path of SDPA without IIN can be derived as ZL/(1 + Vaux/Vmain) (i.e., Zmain) and ZL/(1 + Vmain/Vaux) (i.e., Zaux’), respectively. And LC resonators are added for absorbing device capacitors. Since Vaux gradually increases as the input signal becomes larger, an IIN is required at the output of auxiliary path which makes sure that impedances of both main and auxiliary paths’ output are decreased in this period. Similarly, impedances seen by the output in main and auxiliary path of PDPA without IIN in Fig. 4(b) can be given by ZL ∙ (1 + Iaux/Imain) (i.e., Z′main) and ZL ∙ (1 + Imain/Iaux) (i.e., Zaux), respectively. Note that Iaux gradually increases as the input signal becomes lager, thus IIN is required at the output of main path for two decreasing impedances.
A QTL is the most common way for the physical implementation of IIN but limits the bandwidth of Doherty PA since it is inherently frequency dependent. As the main path is connected directly to the output pad, it minimizes the impact of soft opening from the auxiliary path at deep-PBO status, behaving larger bandwidth compared to parallel power combiner. Moreover, main path can be considered as a current source with high internal impedance according to the device model, which provides an excellent isolation from output pad to auxiliary path and weak frequency-dependent load modulation. Frequence performances of Zmain, which have been already normalized by Z0, for PDPA and SDPA in both deep PBO and saturated status without LC resonators are shown in Fig. 5(a). Besides, frequence performances of Zmain after adding LC resonators in deep PBO and saturated status are shown in Fig. 5(b). Those characteristics further confirm that two-way SDPA is a better choice for wideband applications.
2.3 Bandwidth analysis of impedance inverting network
The layout implementation of IIN is the key matter in the design of SDPA. As the physical length of conventional QTL is too long to be further integrated in multiple-channels phased array system, IINs are commonly designed basing on different kinds of lumped-element model for compact die area. To intuitively get the impedances seen by the outputs of main and auxiliary path under different power status, SDPA shown in Fig. 4(a) is simplified to the form in Fig. 6(a). At 0 dB PBO when both main and auxiliary path are saturated, Zm, Za, and the characteristic Z0 of λ/4 T-line are equal to ZL/2. At 6 dB PBO when main path is just saturated Zm = ZL = 2Z0, and Za can then be derived as Z20/Zm = Z0/2 = RL/4. In this situation, Fig. 6(a) is finally equivalent to a two-port circuit shown in Fig. 6(b).
Fig. 6(c) illustrates impedance inversion paths of different lumped-elements based IINs and ideal λ/4 T-line from 2Z0 to Z0/2. Note that Smith chart is normalized by the value of Z0. Referring to the specific values of the lumped components shown in Fig. 6(d) and the simulated S21 and S11 plotted in Fig. 7, the advantages of theoretical multi-step L−C network can be well illustrated by the following two points.
(1) Wider bandwidth: The smallest theoretically achievable Q factor of multi-step L−C network is approximately 0.78, which is almost two fifths the Q factor of single-step IIN. Meanwhile, it performs a close Q factor to ideal λ/4 T-Line, indicating an excellent wideband impedance inverting performance as shown in Fig. 7.
(2) More likely compact layout: Under the same Q factor, values of the lumped components in multi-step L−C network is about a quarter to a third that of multi-step C−L network, behaving an easier and more compact layout implementation when transformer-based impedance matching networks are used.
3. Topology of the proposed SDPA
3.1 The implementation of distributed IIN and series power combiner
A high-order distributed IIN is employed in the proposed SDPA for broadband load modulation. In the actual design, parasitic capacitor Cp in auxiliary path can no longer be ignored, equated to an additional element connecting parallelly at the source terminal shown in Fig. 6(b). In this case, IIN is commonly designed as a more general multi-step C−L−C π network in the replacement of the theoretical multi-step L−C network shown in Fig. 6(d). Equivalence relation between the single-step C−L−C π network and the transmission line can be expressed as in Fig. 8(a)[17]. Note that phase shift of each step is supposed to be designed the same as θn = 90°/n for bandwidth improvement in n-step C−L−C π network.
The specific implementation procedure of the proposed multi-step distributed IIN is shown in Figs. 9(a)−9(c). The shunt capacitor C1 is moved to the first side of the transformer in auxiliary path, regarded as part of parasitic capacitor from devices. The series L1 then absorbed into the leakage inductors of the secondary side of output impedance matching balun (IMB) in auxiliary path. Besides, the second step of IIN is replaced by a coupler-based network, in which C3 acts as a coupling capacitor. Finally, the series L3 is absorbed into the leakage inductor of the secondary side of IMB in the main path and C4 is removed for phase alignment. Equivalence from single-step C−L−C π network to the lumped-element model of transformer and coupler-based network can be expressed as in Figs. 8(b)[18] and 8(c)[1, 19], respectively.
Even though the actual parasitic parameters increase the complexity of impedance matching, resulting in the impedance inversion path of the actual IIN network being closer to the boundary in the Smith chart and indicating a bigger Q factor than that of multi-step L−C IIN in Fig. 6(c), the proposed distributed multi-step IIN still exhibits relatively impressive broadband 90° phase shift performance and excellent AM−PM characteristics. As shown in Figs. 10(a) and 10(b), the phase deviation of the proposed IIN is less than 15° in the range of 21.5-to-37 GHz and in the range of 23.5-to-33 GHz at 6 dB PBO and 0 dB PBO states, respectively. The AM–PM distortion is illustrated in Fig. 10(c), showing a good linear performance of the proposed SDPA. Moreover, the simulated relationship between effective load impedances seen by both main and auxiliary paths and normalized output power at different frequencies are shown in Figs. 11(a)−11(d), indicating the load modulation operation of the two-way Doherty PA.
The EM model of the SDPA power combiner network is shown in Fig. 12. It consists of two transformers and a coupled-line. Two top layers, M8 and M9, are used in the proposed power combiner, which completes impedance matching with low transmission loss. For output IMB in the main path, the primary inductance is 192 pH with 63.5 μm outer radius while the second inductance is 285 pH with 71 μm outer radius, and the peak Q factor of the primary and secondary inductances are 29.4 and 15.2, respectively. For the output IMB in the auxiliary path, the primary inductance is 203 pH with 61.5 μm outer radius while the second inductance is 230 pH with 58 μm outer radius, and the peak Q factor of the primary and secondary inductances are 21.7 and 10. The coupling coefficients of the output IMBs in auxiliary and main path are also carefully chosen to provide the optimum load Zopt in wideband for output stage, which are 0.71 and 0.48, respectively. Two top layers, M8 and AP, are utilized at the primary coil tap, ensuring the overcurrent capability under large signals. The simulated relationships between passive efficiency of the SDPA output network and normalized output power at different frequencies are shown in Figs. 13(a)−13(d). Note that the insertion loss calculations for both main and auxiliary paths are subtracted by the intrinsic insertion loss of 3 dB over the entire input power range.
3.2 The overall architecture of SDPA
The detailed schematic of the proposed SDPA is illustrated in Fig. 14(a). A wideband quadrature hybrid coupler (QHC) is employed before the driver stage to generate 90° difference between main and auxiliary path of SDPA. In this work, a hybrid-based structure is used for lower insertion losses compared to polyphase filter (PPF)[20] and more excellent wideband quadrature performance compared quadrature all-pass filter (QAF)[21]. To be specific, a helical structure is employed for a compact layout and two top layers, M9 and M8, are used for small capacitance and inductance parasitism. The EM model of the QHC is shown in Fig. 15(a).
Two common-source amplification stages are adopted both in main and auxiliary paths. The sizes of transistors in the driver stage and the power stage are 80 μm/60 nm and 160 μm/60 nm respectively. Two stages of main path are biased at class-AB for better linearity before saturation. To ensure the stability over the entire operating band, neutralization capacitors are also utilized, with the capacitor values of 29 fF for driver amplifier and 57 fF for power amplifier. Meanwhile, both driver amplifier and power amplifier of the auxiliary path are biased through adaptive bias network (ABN), whose output voltages reach class-AB bias level at saturation. ABN contains an envelope detector and a bias control circuit, first of which reversely extracts the envelope of input signal while second of which further amplifies the signal in reverse, making the output voltage of ABN adjusted adaptively with the input signal. As shown in Fig. 14(c), the simulated BW−3dB of ABN is 1.59 GHz. Finally, a wideband power combiner is designed to complete impedance inversion and matching operations.
To realize a flat S21 for the proposed SDPA, the input and inter IMBs are designed with opposite gain-frequency curve characteristics. Their EM models are shown in Figs. 15(b) and 15(c). Three thick metal layers, including M8, M9, and AP, are used to implement the passive networks. For the input IMBs in the main and auxiliary paths, the primary inductance is 154 pH with 45 μm outer radius while the second inductance is 336 pH with 33.5 μm outer radius, and the peak Q factors of the primary and secondary inductances are 23.3 and 29.3, respectively. For the inter IMBs in the main and auxiliary paths, the primary inductance is 542 pH with 73 μm outer radius while the second inductance is 255 pH with 59 μm outer radius, and the peak Q factor of the primary and secondary inductances are 21.3 and 14.6, respectively.
4. Measurement results
The proposed SDPA is fabricated in 65 nm bulk CMOS technology, with 0.28 mm2 core area and 0.53 mm2 full area (including Pads). Its die micrograph is exhibited in Fig. 16. Under 1-V power supply, the overall static power consumption is 97 mW.
4.1 Continuous-wave measurement results
The S-parameter characteristics are measured by Keysight N5247B network analyzer. As depicted in Fig. 17, the peak gain is 21.2 dB at 34.2 GHz with a 3 dB bandwidth from 21.5 to 37 GHz. Besides, the measured S11 is lower than −7.3 dB and S22 is lower than −6 dB in 3 dB bandwidth. Note that the measurement setup of small signals is exhibited in Fig. 18(a) and the insertion loss of probes and cables are measured and de-embedded.
Large signal characteristics of the proposed Doherty PA are measured by Keysight U8487A power meter. The measurement setup is exhibited in Fig. 18(b). Note that the insertion loss of probes and cables are obtained from the specific measured S-parameter files provided by the producer. Limiting by the available signal generator, results only cover frequencies below 30 GHz. The broadband linear and efficiency enhancing performance of SDPA are depicted in Fig. 19 and Fig. 20, respectively. Across 21 to 30 GHz, the OP1dB is over 13.4 dBm and the Psat is over 16 dBm. In the same band mentioned above, the peak, OP1dB, and 6dBPBO PAEs of SDPA are over 20.4%, 16.2%, and 9%, respectively. Besides, the maximum measured Psat is 17.5 dBm and the maximum measured OP1dB is 14.7 dBm. Its maximum measured peak, OP1dB, and 6dBPBO PAEs are 28.2%, 23.2%, and 13.2%, respectively. The measured CW results of power gain and PAE versus Pout at different frequencies are also plotted in Figs. 21(a)−21(d), showing over two times efficiency enhancement at 6dBPBO compared with an ideal class-A PA, and about 1.3 times efficiency enhancement at OP1dB compared with an ideal class-B PA.
4.2 Modulated signal measurement results
Keysight M8195A is used as the arbitrary waveform generator and Keysight UXR0594A is used as the real-time oscilloscope in the measurement under modulated signals, using Keysight M8195A as the arbitrary waveform generator and Keysight UXR0594A as the real-time oscilloscope. The measurement setup is exhibited in Fig. 18(c). Without digital pre-distortion (DPD) and equalization, EVMs are lower than −25.2 dB for 200 MHz 64-QAM signals between 22 and 31 GHz. Besides, the proposed SDPA achieves −33.35, −23.52, and −20 dB EVMs for 100 MHz 256-QAM, 600 MHz 64-QAM and 2 GHz 16-QAM signals at 27 GHz without DPD and equalization. The measured constellations and spectrums under different kinds and frequencies of modulated signals are illustrated in Fig. 22 and Fig. 23.
5. Conclusion
This paper presents a K/Ka-band Doherty PA manufactured in 65 nm bulk CMOS technology. Consisting a series power combiner with a distributed IIN, the proposed DPA realized a wideband performance of linear and efficiency enhancement. The measured Psat and OP1dB are over 16 dBm and 13.4 dBm under 1-V power supply and across 21 to 30 GHz. In the same condition, its measured peak, OP1dB, and 6dBPBO PAE results are over 20.4%, 16.2%, and 9%. Besides, the maximum measured PAEs at peak, OP1dB, and 6dBPBO are 28.2%, 23.2%, and 13.2%, respectively. The maximum measured Psat is 17.5 dBm and the maximum measured OP1dB is 14.7 dBm. Table 1 summarizes the performance of this work and compares it with other prior-art Doherty PA designs.
| Design parameters | RFIC 2017[22] | TMTT 2020[23] | TCAS-II 2021[24] | This work |
| Topology | Two-way PDPA | Two-way PDPA | Two-way PDPA | Two-way SDPA |
| Technology | 28 nm bulk | 45 nm SOI | 65 nm bulk | 65 nm bulk |
| Supply (V) | 1 | 1.5 | 2 | 1 |
| 3 dB bandwidth (GHz) | 29−35*(18.8%) | 25.5−36*(34.1%) | 25.6−29.4(13.8%) | 21.5−37(53.0%) |
| Core area (mm2) | 0.59 | 1.5 | 0.35 | 0.28 |
| Max gain (dB) | 22 | 16.8 | 20.4 | 21.2 |
| Psat (dBm) | 19.8 | 18.2 | 17.5 | 17.5 |
| OP1dB (dBm) | 16 | 15.7 | 17 | 14.7 |
| PAEmax (%) | 21 | 22 | 27 | 28.2 |
| PAE@OP1dB (%) | 12.8 | 16.5 | 27* | 23.2 |
| PAE@6dBPBO (%) | 9 | 9.5 | 18.7 | 13.2 |
| *Graphically estimated. | ||||
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Acknowledgments
This work was supported in part by the National Key Research and Development Program of China under Grant 2020YFB1807300 and in part by the Beijing Advanced Innovation Center for Integrated Circuits.
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