Optimizing 55 nm split-gate memory for compute-in-memory: a focus on floating-gate engineering

Wanyi Ling; Ranran Liu; Kun Ren; Dianyu Qi; Yongyu Wu; Guangji Li; Miao Zhou; Qingshuang Xu; Zhenghui Xia; Xuan Li; Dertsyr Fan; Ichun Chuang; TzungWen Cheng; Chenming Tsai; Dawei Gao

doi:10.1088/1674-4926/25060033

J. Semicond. > Just Accepted

ARTICLES

Optimizing 55 nm split-gate memory for compute-in-memory: a focus on floating-gate engineering

Wanyi Ling¹, Ranran Liu¹, Kun Ren^1,, Dianyu Qi^1,, Yongyu Wu², Guangji Li², Miao Zhou², Qingshuang Xu², Zhenghui Xia², Xuan Li², Dertsyr Fan³, Ichun Chuang³, TzungWen Cheng³, Chenming Tsai³ and Dawei Gao^{1, 2}

+ Author Affiliations

Corresponding author: Kun Ren, kun.ren@zju.edu.cn; Dianyu Qi, qidianyu@zju.edu.cn

DOI: 10.1088/1674-4926/25060033CSTR: 32376.14.1674-4926.25060033

References

[1]	Yu S M, Jiang H W, Huang S S, et al. Compute-in-memory chips for deep learning: Recent trends and prospects. IEEE Circuits Syst Mag, 2021, 21(3), 31 doi: 10.1109/MCAS.2021.3092533
[2]	Peng X C, Huang S S, Jiang H W, et al. DNN NeuroSim V2.0: An end-to-end benchmarking framework for compute-in- memory accelerators for on-chip training. IEEE Trans Comput Aided Des Integr Circuits Syst, 2021, 40(11), 2306 doi: 10.1109/TCAD.2020.3043731
[3]	Yu S M, Shim W, Peng X C, et al. RRAM for compute-in-memory: From inference to training. IEEE Trans Circuits Syst I Regul Pap, 2021, 68(7), 2753 doi: 10.1109/TCSI.2021.3072200
[4]	Chang L, Ma X, Wang Z H, et al. DASM: Data-streaming-based computing in nonvolatile memory architecture for embedded system. IEEE Trans Very Large Scale Integr VLSI Syst, 2019, 27(9), 2046 doi: 10.1109/TVLSI.2019.2912941
[5]	Sun X, Khwa W S, Chen Y S, et al. PCM-based analog compute-In-memory: Impact of device non-idealities on inference accuracy. IEEE Trans Electron Devices, 2021, 68(11), 5585 doi: 10.1109/TED.2021.3113300
[6]	Khwa W S, Chen J J, Li J F, et al. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55. 8TOPS/W fully parallel product-sum operation for binary DNN edge processors, ISSCC, 2018, 8310401, 496
[7]	Lo Y C, Liu R S. Morphable CIM: Improving operation intensity and depthwise capability for SRAM-CIM architecture. 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, 1
[8]	Do N, Van Tran H, Kotov A, et al. Split-gate floating poly SuperFlash® memory technology, design, and reliability. Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations. Cham: Springer International Publishing, 2017, 131
[9]	Yook C G, Kim J N, Kim Y, et al. Design strategies of 40 nm split-gate NOR flash memory device for low-power compute-in-memory applications. Micromachines, 2023, 14(9), 1753 doi: 10.3390/mi14091753
[10]	Feng Y, Sun Z H, Qi Y R, et al. Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance. J Semicond, 2024, 45(1), 012301 doi: 10.1088/1674-4926/45/1/012301
[11]	Feng Y, Chen B, Tang M F, et al. Near-threshold-voltage operation in flash-based high-precision computing-in-memory to implement Poisson image editing. Sci China Inf Sci, 2023, 66(12), 222402 doi: 10.1007/s11432-022-3743-x
[12]	Zhou Y J, Shao H Y, Zhu R T, et al. Hybrid-FE-layer FeFET with high linearity and endurance toward on-chip CIM by array demonstration. IEEE Electron Device Lett, 2024, 45(2), 276 doi: 10.1109/LED.2023.3346030
[13]	Jerry M, Dutta S, Kazemi A, et al. A ferroelectric field effect transistor based synaptic weight cell. J Phys D: Appl Phys, 2018, 51(43), 434001 doi: 10.1088/1361-6463/aad6f8
[14]	Lue H T, Hu H W, Hsu T H, et al. Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, 1
[15]	Zhang X R, Huang J, Liu X P, et al. An adaptive read control voltage scheme for reliability enhancement of flash-based in-memory computing architecture for neural network. IEEE Trans Device Mater Reliab, 2024, 24(3), 422 doi: 10.1109/TDMR.2024.3429662

Fig. 1. (Color online) (a) Schematic process flow; (b) Cross-sectional TEM of “L”-shaped flash memory.

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) Structure and performance of “L”-shaped flash memory obtained from full process and device simulation.

DownLoad: Full-Size Img PowerPoint

Fig. 3. (Color online) (a) Programming operation by source-side injection (SSI) with band diagram; (b) Erase operation by Fowler-Nordheim (FN) tunneling with band diagram.

DownLoad: Full-Size Img PowerPoint

Fig. 4. (Color online) (a) Schematic representation of a flash-based CIM architecture; (b) Detailed illustration of an “L”-shaped split-gate NOR flash memory array.

DownLoad: Full-Size Img PowerPoint

Fig. 5. (Color online) Characterization of the "L"-shaped split-gate NOR flash memory's multi-state conductive behavior (real experimental data): (a) Conductance variation under identical pulse scheme; (b) Conductance changes with linearly varying amplitude pulses; (c) Conductance evolution with varying voltage and pulse width.

DownLoad: Full-Size Img PowerPoint

Fig. 6. (Color online) VGG8 Network for Image Recognition: Accuracy Evaluation Using CIFAR-10 Dataset.

DownLoad: Full-Size Img PowerPoint

Fig. 7. (Color online) (a) I_BL-V_CG curves after programming and erasing operations for “L”- shaped split-gate floating gate memories with three FG lengths (110/ 95/ 80 nm); (b) Threshold voltages and operating windows extracted from I_BL-V_CG curves.

DownLoad: Full-Size Img PowerPoint

Fig. 8. (Color online)The Potentiation and Depression Processes of Conductance with VWPS Pulse Mechanism for Devices with Different FG Lengths: (a) 110nm, (b) 95nm, (c) 80nm.

DownLoad: Full-Size Img PowerPoint

Fig. 9. (Color online) Weight Update Fitting of “L”-shaped Split-Gate Devices with Optimized Parameter A: (a) 110 nm FG Length, (b) 95 nm FG Length, (c) 80 nm FG Length (R² > 0.96); (d) Training accuracy on DNN+NeuroSim Framework V2.0 for Devices with Three FG Lengths.

DownLoad: Full-Size Img PowerPoint

Table 1. Performance comparison of split-gate eFlash in 55 nm node

	this paper	SST ESF3
node (nm)	55	55
byte/word program time (μs)	8-10	16
program voltage (V)	7	10
page/sector erase time (ms)	2	20
erase voltage (V)	12	11-13
cell read voltage (V)	1.5	2.5
cell size (μm²)	0.078	0.09

DownLoad: CSV

Table 2. Main NeuroSim simulation options

DNN+NeuroSim Framework V2.0
dataset	CIFAR-10
network	VGG-8
weight precision	5
ADC precision	5
activation precision	5
resistance On/Off	experimental resistance on/off data
nonlinear weight update	MATLAB-fit LTP/LTD nonlinear Params
device-to-device	0
cycle-to-cycle	0

DownLoad: CSV

[1]	Yu S M, Jiang H W, Huang S S, et al. Compute-in-memory chips for deep learning: Recent trends and prospects. IEEE Circuits Syst Mag, 2021, 21(3), 31 doi: 10.1109/MCAS.2021.3092533
[2]	Peng X C, Huang S S, Jiang H W, et al. DNN NeuroSim V2.0: An end-to-end benchmarking framework for compute-in- memory accelerators for on-chip training. IEEE Trans Comput Aided Des Integr Circuits Syst, 2021, 40(11), 2306 doi: 10.1109/TCAD.2020.3043731
[3]	Yu S M, Shim W, Peng X C, et al. RRAM for compute-in-memory: From inference to training. IEEE Trans Circuits Syst I Regul Pap, 2021, 68(7), 2753 doi: 10.1109/TCSI.2021.3072200
[4]	Chang L, Ma X, Wang Z H, et al. DASM: Data-streaming-based computing in nonvolatile memory architecture for embedded system. IEEE Trans Very Large Scale Integr VLSI Syst, 2019, 27(9), 2046 doi: 10.1109/TVLSI.2019.2912941
[5]	Sun X, Khwa W S, Chen Y S, et al. PCM-based analog compute-In-memory: Impact of device non-idealities on inference accuracy. IEEE Trans Electron Devices, 2021, 68(11), 5585 doi: 10.1109/TED.2021.3113300
[6]	Khwa W S, Chen J J, Li J F, et al. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55. 8TOPS/W fully parallel product-sum operation for binary DNN edge processors, ISSCC, 2018, 8310401, 496
[7]	Lo Y C, Liu R S. Morphable CIM: Improving operation intensity and depthwise capability for SRAM-CIM architecture. 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, 1
[8]	Do N, Van Tran H, Kotov A, et al. Split-gate floating poly SuperFlash® memory technology, design, and reliability. Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations. Cham: Springer International Publishing, 2017, 131
[9]	Yook C G, Kim J N, Kim Y, et al. Design strategies of 40 nm split-gate NOR flash memory device for low-power compute-in-memory applications. Micromachines, 2023, 14(9), 1753 doi: 10.3390/mi14091753
[10]	Feng Y, Sun Z H, Qi Y R, et al. Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance. J Semicond, 2024, 45(1), 012301 doi: 10.1088/1674-4926/45/1/012301
[11]	Feng Y, Chen B, Tang M F, et al. Near-threshold-voltage operation in flash-based high-precision computing-in-memory to implement Poisson image editing. Sci China Inf Sci, 2023, 66(12), 222402 doi: 10.1007/s11432-022-3743-x
[12]	Zhou Y J, Shao H Y, Zhu R T, et al. Hybrid-FE-layer FeFET with high linearity and endurance toward on-chip CIM by array demonstration. IEEE Electron Device Lett, 2024, 45(2), 276 doi: 10.1109/LED.2023.3346030
[13]	Jerry M, Dutta S, Kazemi A, et al. A ferroelectric field effect transistor based synaptic weight cell. J Phys D: Appl Phys, 2018, 51(43), 434001 doi: 10.1088/1361-6463/aad6f8
[14]	Lue H T, Hu H W, Hsu T H, et al. Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, 1
[15]	Zhang X R, Huang J, Liu X P, et al. An adaptive read control voltage scheme for reliability enhancement of flash-based in-memory computing architecture for neural network. IEEE Trans Device Mater Reliab, 2024, 24(3), 422 doi: 10.1109/TDMR.2024.3429662

Search

GET CITATION

shu

Export: BibTex EndNote

Article Metrics

Article views: 9 Times PDF downloads: 2 Times Cited by: 0 Times

History

Received: 27 June 2025 Revised: 26 July 2025 Online: Accepted Manuscript: 20 September 2025

Article Navigation > Journal of Semiconductors > 2025 > Accepted Manuscript

Wanyi Ling, Ranran Liu, Kun Ren, Dianyu Qi, Yongyu Wu, Guangji Li, Miao Zhou, Qingshuang Xu, Zhenghui Xia, Xuan Li, Dertsyr Fan, Ichun Chuang, TzungWen Cheng, Chenming Tsai, Dawei Gao. Optimizing 55 nm split-gate memory for compute-in-memory: a focus on floating-gate engineering[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/25060033 ****W Y Ling, R R Liu, K Ren, D Y Qi, Y Y Wu, G J Li, M Zhou, Q S Xu, Z H Xia, X Li, D Fan, I Chuang, T Cheng, C Tsai, and D W Gao, Optimizing 55 nm split-gate memory for compute-in-memory: a focus on floating-gate engineering[J]. J. Semicond., 2025, accepted doi: 10.1088/1674-4926/25060033

Citation:

W Y Ling, R R Liu, K Ren, D Y Qi, Y Y Wu, G J Li, M Zhou, Q S Xu, Z H Xia, X Li, D Fan, I Chuang, T Cheng, C Tsai, and D W Gao, Optimizing 55 nm split-gate memory for compute-in-memory: a focus on floating-gate engineering[J]. J. Semicond., 2025, accepted doi: 10.1088/1674-4926/25060033

Citation:

PDF( 9048 KB)

Optimizing 55 nm split-gate memory for compute-in-memory: a focus on floating-gate engineering

DOI: 10.1088/1674-4926/25060033

CSTR: 32376.14.1674-4926.25060033

1.
College of Integrated Circuits, Zhejiang University, Hangzhou 310000, China
2.
Zhejiang ICsprout Semiconductor, Hangzhou 311200, China
3.
IOTMemory Technology Inc., Taipei City 10592, China

More Information

Wanyi Ling received her Bachelor's and Master's degrees in Materials Science from Sichuan University. She is currently pursuing her PhD in Integrated Circuit Engineering at Zhejiang University. Her research focuses on process optimization and device design of novel split-gate floating-gate memory
Kun Ren received his PhD from the University of Chinese Academy of Sciences and his Bachelor's degree from Fudan University. He is a Senior Research Fellow and PhD Supervisor at Zhejiang University, focusing on computational lithography EDA, and embedded memory design-process co-optimization
Dianyu Qi received his Ph.D. from East China University of Science and Technology in 2015. He is currently a Senior Research Fellow at the Hangzhou Global Scientific and Technological Innovation Center, Zhejiang University, China. His research focuses on novel semiconductor materials and devices
Corresponding author: kun.ren@zju.edu.cn; qidianyu@zju.edu.cn
Received Date: 2025-06-27
Revised Date: 2025-07-26

Available Online: 2025-09-20

Abstract

FullText(HTML)

References(15)