Fig. 1.
(Color online) Illustration of (a) conventional DDIC and (b) RRAM-based DDIC.
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Journal of Semiconductors
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2025
> Accepted Manuscript
| Citation: |
Zhenchao Sui, Yanqing Wu, Zhichao Lv, Xing Zhang. Synergistic performance and yield improvement of embedded RRAM product through process optimization in 40 nm CMOS platform[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/25100021
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Z C Sui, Y Q Wu, Z C Lv, and X Zhang, Synergistic performance and yield improvement of embedded RRAM product through process optimization in 40 nm CMOS platform[J]. J. Semicond., 2025, accepted doi: 10.1088/1674-4926/25100021
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Synergistic performance and yield improvement of embedded RRAM product through process optimization in 40 nm CMOS platform
DOI: 10.1088/1674-4926/25100021
CSTR: 32376.14.1674-4926.25100021
More Information-
Zhenchao Sui got his BS from Xi'an University of Technology in 2003 and MS from Peking University in 2008. He is now a PhD student at Peking University under the supervision of Prof. Xing Zhang. His research focus is on the performance and yield improvement of embedded-RRAM in CMOS platform -
Xing Zhang got his BS from Nanjing University in 1986, M.S. and Ph.D. degree from Shanxi Institute of Microelectronics, China, in 1989 and 1993, respectively. He joined Peking University in 1993 and is now a professor. His current research interests include the physics and novel structures of nano-scaled MOS devices, model and simulation, CMOS Integrated Circuit design and Manufacturing technology - Corresponding author: zhx@pku.edu.cn
- Revised Date: 2025-12-01 Available Online: 2025-12-25
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Abstract
To address the challenges of complexity, power consumption, and cost constraints in traditional display driver integrated circuits (DDICs) caused by external NOR Flash and SRAM, this work proposes an embedded resistive random-access memory (RRAM) integration solution based on a 40 nm high-voltage CMOS logic platform. Targeting the yield fluctuations and stability challenges during RRAM mass production, systematic process optimizations are implemented to achieve synergistic improvements in RRAM performance and yield. Through modifications to the film sputtering and pre-deposition treatment, the within-wafer resistance uniformity (RSU) of the oxygen-deficient layer (ODL) thin film is improved from 11% to 8%, while inter-wafer process stability variation reduces from 23% to below 6%. Consequently, the yield of 8 Mb RRAM embedded mass production products increases from 87% to 98.5%. In terms of device performance, the RRAM demonstrates a fast 4.8 ns read speed, exceptional read disturb immunity of 3 × 108 cycles at 95 °C, 103 write/erase endurance cycles for the 1 Mb cells, and data retention of 12.5 years at 125 °C. Post high-temperature operating life (HTOL) testing exhibits stable high/low resistance window. This study provides process optimization strategies and a reliability assurance framework for the mass production of highly integrated, low-power embedded RRAM display driver IC. -
References
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