Gate oxide damage and synergistic effect on the breakdown voltage under reverse bias stress for SiC MOSFET

Fanpeng Zeng; Yingxin Cui; Zhixin Liu; Zicheng Lu; Lingling Lai; Shoulai Gong; Haochen Wang; Peng Dong; Jisheng Han

doi:10.1088/1674-4926/25110026

J. Semicond. > Just Accepted

ARTICLES

Gate oxide damage and synergistic effect on the breakdown voltage under reverse bias stress for SiC MOSFET

Fanpeng Zeng¹, Yingxin Cui^1,, Zhixin Liu¹, Zicheng Lu¹, Lingling Lai¹, Shoulai Gong¹, Haochen Wang², Peng Dong^2, and Jisheng Han¹

+ Author Affiliations

Corresponding author: Yingxin Cui, cuiyingxin@sdu.edu.cn; Peng Dong, dongpeng0711@foxmail.com

DOI: 10.1088/1674-4926/25110026CSTR: 32376.14.1674-4926.25110026

Abstract: High-temperature reverse bias (HTRB) is one of the most critical reliability for SiC MOSFET, and the termination region is widely regarded as the sensitive area under HTRB stress. Interestingly, through systematically monitoring of the degradation behavior of static electrical parameters under different voltage, this study reveals that the elevated reverse bias (ERB) stress can also induce damage in the gate oxide, which results in the hole trapping and a negative shift of the threshold voltage. Deep level transient spectroscopy (DLTS) measurements were performed and shown that the interface trap density in the gate oxide is promoted after ERB stress. Surprisingly, the reverse leakage current after ERB stress is significantly deteriorated at a gate bias of 0 V, while effectively suppressed by applying a negative gate bias (−5 V), which point to the synergistic effects of channel region on the breakdown voltage. Based on the gate oxide degradations and TCAD simulations, it is elucidated that the trapped positive interface charges in gate oxide cause band bending, leading to the formation of an electron accumulation layer in the channel region at 0 V gate bias and thus resulting in a dominant leakage path. This work reveals the impact and mechanism of the ERB stress induced gate oxide damage on the breakdown voltage and highlights the importance of gate oxide protection, which is of great significance for improving the reliability of SiC MOSFETs in elevated voltage applications.

Key words: elevated reverse bias stress, gate oxide degradation, synergistic effect, interface traps, SiC MOSFET.

References

[1]	She X, Huang A Q, Lucia O, et al. Review of silicon carbide power devices and their applications. IEEE Trans Ind Electron, 2017, 64(10): 8193 doi: 10.1109/TIE.2017.2652401
[2]	Saito W. A future outlook of power devices from the viewpoint of power electronics trends. IEEE Trans Electron Devices, 2024, 71(3): 1356 doi: 10.1109/TED.2023.3332611
[3]	Hazra S, De A K, Cheng L, et al. High switching performance of 1700V, 50A SiC power MOSFET over Si IGBT/BiMOSFET for advanced power conversion applications. IEEE Trans Power Electron, 2015: 1
[4]	Kumar A, Moradpour M, Losito M, et al. Wide band gap devices and their application in power electronics. Energies, 2022, 15(23): 9172 doi: 10.3390/en15239172
[5]	Millán J, Godignon P, Perpiñà X, et al. A survey of wide bandgap power semiconductor devices. IEEE Trans Power Electron, 2014, 29(5): 2155 doi: 10.1109/TPEL.2013.2268900
[6]	Wang H, Blaabjerg F. Power electronics reliability: State of the art and outlook. IEEE J Emerg Sel Topics Power Electron, 2021, 9(6): 6476 doi: 10.1109/JESTPE.2020.3037161
[7]	Lutz J, Schlangenotto H, Scheuermann U, et al. Semiconductor Power Devices: Physics, Characteristics, Reliability. Springer, 2011
[8]	Jayant Baliga B. Silicon Carbide Power Devices. World Scientific, 2006
[9]	Yuan X B, Laird I, Walder S. Opportunities, challenges, and potential solutions in the application of fast-switching SiC power devices and converters. IEEE Trans Power Electron, 2021, 36(4): 3925 doi: 10.1109/TPEL.2020.3024862
[10]	Du Y J, Li J Y, Wang P, et al. Comparison of high voltage SiC MOSFET and Si IGBT power module thermal performance. Mater Sci Forum, 2019, 954: 194 doi: 10.4028/www.scientific.net/MSF.954.194
[11]	Rahimo M. Performance evaluation and expected challenges of silicon carbide power MOSFETs for high voltage applications. Mater Sci Forum, 2017, 897: 649 doi: 10.4028/www.scientific.net/MSF.897.649
[12]	Wei J X, Wei Z X, Fu H, et al. Review on the reliability mechanisms of SiC power MOSFETs: A comparison between planar-gate and trench-gate structures. IEEE Trans Power Electron, 2023, 38(7): 8990 doi: 10.1109/TPEL.2023.3265864
[13]	Salmen P, Friedrichs P. Qualifying a silicon carbide power module: Reliability testing beyond the standards of silicon devices. CIPS 2022; 12th International Conference on Integrated Power Electronics Systems. Berlin, Germany. VDE, 2022: 1
[14]	Moultif N, Joubert E, Masmoudi M, et al. Characterization of HTRB stress effects on SiC MOSFETs using photon emission spectral signatures. Microelectron Reliab, 2017, 76: 243. doi: 10.1016/j.microrel.2017.07.013
[15]	Tang J Y, Duan Y H, Liu P. Investigation of degradation and failure mechanism in 1200 V planar SiC MOSFET under statical accelerated lifetime Test. IEEE Trans Device Mater Relib, 2025, 25(3): 441. doi: 10.1109/TDMR.2025.3577612
[16]	Matsushima H, Yamada R, Shima A. Two mechanisms of charge accumulation in edge termination of 4H-SiC diodes caused by high-temperature bias stress and high-temperature and high-humidity bias stress. IEEE Trans Electron Devices, 2018, 65(8): 3318 doi: 10.1109/TED.2018.2845376
[17]	Dong P, Li P, Zhang L, et al. Atomistic mechanism of 4H-SiC/SiO₂ interface carrier-trapping effects on breakdown-voltage degradation in power devices. Phys Rev Appl, 2021, 15(3): 034007 doi: 10.1103/PhysRevApplied.15.034007
[18]	Yu M Y, Shen Y, Ma H P, et al. Experiment and analysis of termination robustness design for 1200 V 4H-SiC MOSFET. Nanomaterials, 2025, 15(11): 805 doi: 10.3390/nano15110805
[19]	Fiorenza P, Alessandrino M S, Carbone B, et al. Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress. Nanotechnology, 2020, 31(12): 125203 doi: 10.1088/1361-6528/ab5ff6
[20]	Fiorenza P, Adamo S, Alessandrino M S, et al. Correlation between MOSFETs breakdown and 4H-SiC epitaxial defects. 2021 IEEE International Reliability Physics Symposium (IRPS), 2021: 1
[21]	Senzaki J, Kojima K, Kato T, et al. Correlation between reliability of thermal oxides and dislocations in n-type 4H-SiC epitaxial wafers. Appl Phys Lett, 2006, 89(2): 022909 doi: 10.1063/1.2221525
[22]	Jouha W, Masmoudi M, El Oualkadi A, et al. Physical study of SiC power MOSFETs towards HTRB stress based on C-V characteristics. IEEE Trans Device Mater Relib, 2020, 20(3): 506 doi: 10.1109/TDMR.2020.2999029
[23]	Ren M, Liang S Q, Zhou T, et al. Gate oxide failure mechanisms of SiC MOSFET related to electro-thermomechanical stress under HTRB and HTGB test. 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD). Bremen, Germany. IEEE, 2024: 208
[24]	Garete A J, Li Z W, Fung Y W, et al. Reliability performance study of molding compounds on high voltage molded leaded package. 2023 18th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). Taipei, China. IEEE, 2023: 67
[25]	Ooi A L, Goh D, Ngwan V C. High temperature reverse bias (HTRB) & temperature humidity bias (THB) reliability failure mechanisms and improvements in trench power MOSFET and IGBT. IEEE J Electron Devices Soc, 2021, 9: 1181 doi: 10.1109/JEDS.2021.3109347
[26]	Potera R R, Witt T, Zheng Y. Analysis of transient HTRB leakage in a SiC field ring termination. 2020 IEEE International Reliability Physics Symposium (IRPS). Dallas, TX, USA. IEEE, 2020: 1
[27]	Aichinger T, Rescher G, Pobegen G. Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs. Microelectron Reliab, 2018, 80: 68 doi: 10.1016/j.microrel.2017.11.020
[28]	JEDEC Solid State Technology Association. JEP-183A: Guidelines for Measuring the Reliability of Solid-State Drives (SSDs). JEDEC Standard, 2023
[29]	Cai J H, Peng Y J, Fan J F, et al. The reverse bias reliability of SiC MOSFET under different conditions and failure analysis. 2024 25th International Conference on Electronic Packaging Technology (ICEPT). Tianjin, China. IEEE, 2024: 1
[30]	Chowdhury S, Matocha K, Powell B, et al. Next generation 1200V, 3.5mΩ. cm2 SiC planar gate MOSFET with excellent HTRB reliability. 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018: 427
[31]	Rudenko T E, Osiyuk I N, Tyagulski I P, et al. Interface trap properties of thermally oxidized n-type 4H–SiC and 6H–SiC. Solid State Electron, 2005, 49(4): 545 doi: 10.1016/j.sse.2004.12.006
[32]	Jiang S, Zhang M, Meng X W, et al. Trap characterization of trench-gate SiC MOSFETs based on transient drain current. IEEE Trans Power Electron, 2023, 38(5): 6555 doi: 10.1109/TPEL.2023.3242950

Fig. 1. (Color online) (a) Typical schematic of SiC MOSFET. (b) Appearance of a chip. (c) A device in TO247 package.

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) The electrical characteristic curves at various junction temperatures. (a) Blocking characteristics. (b) Output characteristic (I_DS−V_DS). (c) Transfer characteristic (I_DS−V_GS). (d) Forward conduction characteristics of the body diode. (e) Threshold voltage variation. (f) Pulse waveform for the threshold voltage measurement.

DownLoad: Full-Size Img PowerPoint

Fig. 3. (Color online) The schematic diagram of ERB stress.

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Fig. 4. (Color online) The on-line monitoring of drain−source leakage current during stress.

DownLoad: Full-Size Img PowerPoint

Fig. 5. (Color online) The blocking characteristic curves after reverse bias stress of 1200 V

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Fig. 6. (Color online) The threshold voltage variation curves after reverse bias stress of (a) 1200 V and (b) 960 V.

DownLoad: Full-Size Img PowerPoint

Fig. 7. (Color online) The electrical characteristic curves after ERB stress. (a) Output characteristic (I_DS−V_DS) and (b) transfer characteristic (I_DS−V_GS), (c) forward conduction characteristic of the body diode, (d) gate−source leakage current.

DownLoad: Full-Size Img PowerPoint

Fig. 8. (Color online) (a) DLTS spectra and (b) interface trap density (D_it) distributions in stressed and fresh devices.

DownLoad: Full-Size Img PowerPoint

Fig. 9. (Color online) (a, b) Electric field distribution of gate oxide region in JFET and channel area at V_DS = 960 V and 1200 V with V_GS = 0 V. (c) Electric field strength of gate oxide interface extracted from simulations.

DownLoad: Full-Size Img PowerPoint

Fig. 10. (Color online) (a) Holes tunnelling and capture by SiC/SiO₂ interface traps. (b) Holes trapping induce electron accumulation layers and form channel current path within gate oxide.

DownLoad: Full-Size Img PowerPoint

Fig. 11. (Color online) (a, b) Distribution of total current density and (c, d) carrier density in JFET and channel region under V_DS = 1200 V at V_GS = −5 V and 0 V.

DownLoad: Full-Size Img PowerPoint

Fig. 12. (Color online) The impact ionization at V_DS = 1200 V with (a) N_it = 0 and (b) N_it = 5 × 10¹² cm⁻². The current destiny at V_DS = 1200 V with (c) N_it = 0 and (d) N_it = 5 × 10¹² cm⁻².

DownLoad: Full-Size Img PowerPoint

Table 1. Electrical parameters extraction conditions and typical value.

Parameters	Unit	Extraction Conditions	Typical Value
V_BR	V	V_GS = 0 V, I_DS = 100 μA	1580
I_DSS	nA	V_GS = 0 V, V_DS = 1200 V	2.5
R_DS,on	mΩ	V_GS = 20 V, I_DS = 20 A	83
V_GS,th	V	V_GS = V_DS, I_DS = 5 mA	2.89
V_SD	V	V_GS = 0 V, I_DS = −10 A	−3.60

DownLoad: CSV

[1]	She X, Huang A Q, Lucia O, et al. Review of silicon carbide power devices and their applications. IEEE Trans Ind Electron, 2017, 64(10): 8193 doi: 10.1109/TIE.2017.2652401
[2]	Saito W. A future outlook of power devices from the viewpoint of power electronics trends. IEEE Trans Electron Devices, 2024, 71(3): 1356 doi: 10.1109/TED.2023.3332611
[3]	Hazra S, De A K, Cheng L, et al. High switching performance of 1700V, 50A SiC power MOSFET over Si IGBT/BiMOSFET for advanced power conversion applications. IEEE Trans Power Electron, 2015: 1
[4]	Kumar A, Moradpour M, Losito M, et al. Wide band gap devices and their application in power electronics. Energies, 2022, 15(23): 9172 doi: 10.3390/en15239172
[5]	Millán J, Godignon P, Perpiñà X, et al. A survey of wide bandgap power semiconductor devices. IEEE Trans Power Electron, 2014, 29(5): 2155 doi: 10.1109/TPEL.2013.2268900
[6]	Wang H, Blaabjerg F. Power electronics reliability: State of the art and outlook. IEEE J Emerg Sel Topics Power Electron, 2021, 9(6): 6476 doi: 10.1109/JESTPE.2020.3037161
[7]	Lutz J, Schlangenotto H, Scheuermann U, et al. Semiconductor Power Devices: Physics, Characteristics, Reliability. Springer, 2011
[8]	Jayant Baliga B. Silicon Carbide Power Devices. World Scientific, 2006
[9]	Yuan X B, Laird I, Walder S. Opportunities, challenges, and potential solutions in the application of fast-switching SiC power devices and converters. IEEE Trans Power Electron, 2021, 36(4): 3925 doi: 10.1109/TPEL.2020.3024862
[10]	Du Y J, Li J Y, Wang P, et al. Comparison of high voltage SiC MOSFET and Si IGBT power module thermal performance. Mater Sci Forum, 2019, 954: 194 doi: 10.4028/www.scientific.net/MSF.954.194
[11]	Rahimo M. Performance evaluation and expected challenges of silicon carbide power MOSFETs for high voltage applications. Mater Sci Forum, 2017, 897: 649 doi: 10.4028/www.scientific.net/MSF.897.649
[12]	Wei J X, Wei Z X, Fu H, et al. Review on the reliability mechanisms of SiC power MOSFETs: A comparison between planar-gate and trench-gate structures. IEEE Trans Power Electron, 2023, 38(7): 8990 doi: 10.1109/TPEL.2023.3265864
[13]	Salmen P, Friedrichs P. Qualifying a silicon carbide power module: Reliability testing beyond the standards of silicon devices. CIPS 2022; 12th International Conference on Integrated Power Electronics Systems. Berlin, Germany. VDE, 2022: 1
[14]	Moultif N, Joubert E, Masmoudi M, et al. Characterization of HTRB stress effects on SiC MOSFETs using photon emission spectral signatures. Microelectron Reliab, 2017, 76: 243. doi: 10.1016/j.microrel.2017.07.013
[15]	Tang J Y, Duan Y H, Liu P. Investigation of degradation and failure mechanism in 1200 V planar SiC MOSFET under statical accelerated lifetime Test. IEEE Trans Device Mater Relib, 2025, 25(3): 441. doi: 10.1109/TDMR.2025.3577612
[16]	Matsushima H, Yamada R, Shima A. Two mechanisms of charge accumulation in edge termination of 4H-SiC diodes caused by high-temperature bias stress and high-temperature and high-humidity bias stress. IEEE Trans Electron Devices, 2018, 65(8): 3318 doi: 10.1109/TED.2018.2845376
[17]	Dong P, Li P, Zhang L, et al. Atomistic mechanism of 4H-SiC/SiO₂ interface carrier-trapping effects on breakdown-voltage degradation in power devices. Phys Rev Appl, 2021, 15(3): 034007 doi: 10.1103/PhysRevApplied.15.034007
[18]	Yu M Y, Shen Y, Ma H P, et al. Experiment and analysis of termination robustness design for 1200 V 4H-SiC MOSFET. Nanomaterials, 2025, 15(11): 805 doi: 10.3390/nano15110805
[19]	Fiorenza P, Alessandrino M S, Carbone B, et al. Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress. Nanotechnology, 2020, 31(12): 125203 doi: 10.1088/1361-6528/ab5ff6
[20]	Fiorenza P, Adamo S, Alessandrino M S, et al. Correlation between MOSFETs breakdown and 4H-SiC epitaxial defects. 2021 IEEE International Reliability Physics Symposium (IRPS), 2021: 1
[21]	Senzaki J, Kojima K, Kato T, et al. Correlation between reliability of thermal oxides and dislocations in n-type 4H-SiC epitaxial wafers. Appl Phys Lett, 2006, 89(2): 022909 doi: 10.1063/1.2221525
[22]	Jouha W, Masmoudi M, El Oualkadi A, et al. Physical study of SiC power MOSFETs towards HTRB stress based on C-V characteristics. IEEE Trans Device Mater Relib, 2020, 20(3): 506 doi: 10.1109/TDMR.2020.2999029
[23]	Ren M, Liang S Q, Zhou T, et al. Gate oxide failure mechanisms of SiC MOSFET related to electro-thermomechanical stress under HTRB and HTGB test. 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD). Bremen, Germany. IEEE, 2024: 208
[24]	Garete A J, Li Z W, Fung Y W, et al. Reliability performance study of molding compounds on high voltage molded leaded package. 2023 18th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). Taipei, China. IEEE, 2023: 67
[25]	Ooi A L, Goh D, Ngwan V C. High temperature reverse bias (HTRB) & temperature humidity bias (THB) reliability failure mechanisms and improvements in trench power MOSFET and IGBT. IEEE J Electron Devices Soc, 2021, 9: 1181 doi: 10.1109/JEDS.2021.3109347
[26]	Potera R R, Witt T, Zheng Y. Analysis of transient HTRB leakage in a SiC field ring termination. 2020 IEEE International Reliability Physics Symposium (IRPS). Dallas, TX, USA. IEEE, 2020: 1
[27]	Aichinger T, Rescher G, Pobegen G. Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs. Microelectron Reliab, 2018, 80: 68 doi: 10.1016/j.microrel.2017.11.020
[28]	JEDEC Solid State Technology Association. JEP-183A: Guidelines for Measuring the Reliability of Solid-State Drives (SSDs). JEDEC Standard, 2023
[29]	Cai J H, Peng Y J, Fan J F, et al. The reverse bias reliability of SiC MOSFET under different conditions and failure analysis. 2024 25th International Conference on Electronic Packaging Technology (ICEPT). Tianjin, China. IEEE, 2024: 1
[30]	Chowdhury S, Matocha K, Powell B, et al. Next generation 1200V, 3.5mΩ. cm2 SiC planar gate MOSFET with excellent HTRB reliability. 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018: 427
[31]	Rudenko T E, Osiyuk I N, Tyagulski I P, et al. Interface trap properties of thermally oxidized n-type 4H–SiC and 6H–SiC. Solid State Electron, 2005, 49(4): 545 doi: 10.1016/j.sse.2004.12.006
[32]	Jiang S, Zhang M, Meng X W, et al. Trap characterization of trench-gate SiC MOSFETs based on transient drain current. IEEE Trans Power Electron, 2023, 38(5): 6555 doi: 10.1109/TPEL.2023.3242950

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Received: 26 November 2025 Revised: 28 December 2025 Online: Accepted Manuscript: 15 January 2026

Article Navigation > Journal of Semiconductors > 2026 > Accepted Manuscript

Fanpeng Zeng, Yingxin Cui, Zhixin Liu, Zicheng Lu, Lingling Lai, Shoulai Gong, Haochen Wang, Peng Dong, Jisheng Han. Gate oxide damage and synergistic effect on the breakdown voltage under reverse bias stress for SiC MOSFET[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/25110026 ****F P Zeng, Y X Cui, Z X Liu, Z C Lu, L L Lai, S L Gong, H C Wang, P Dong, and J S Han, Gate oxide damage and synergistic effect on the breakdown voltage under reverse bias stress for SiC MOSFET[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/25110026

Citation:

F P Zeng, Y X Cui, Z X Liu, Z C Lu, L L Lai, S L Gong, H C Wang, P Dong, and J S Han, Gate oxide damage and synergistic effect on the breakdown voltage under reverse bias stress for SiC MOSFET[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/25110026

Citation:

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Gate oxide damage and synergistic effect on the breakdown voltage under reverse bias stress for SiC MOSFET

DOI: 10.1088/1674-4926/25110026

CSTR: 32376.14.1674-4926.25110026

1.
Institute of novel semiconductors, Shandong University, Jinan 250100, China
2.
Institute of electronic engineering, China Academy of Engineering Physics, Chengdu 610200, China

More Information

Fanpeng Zeng got his bachelor’s degree in 2018 from Yanshan University and his master’s degree in 2024 from Shandong University. Now he is a doctoral student at Shandong University under the supervision of Prof. Yingxin Cui and Prof. Jisheng Han. His research focuses on the reliability study of silicon carbide power devices
Yingxin Cui received her doctoral degree from Shandong University, Jinan, China, in 2016. She is currently a Professor with the Institute of novel semiconductors, Shandong University, Jinan, China. Her current research interests include the material defects in silicon carbide, high reliability silicon carbide power devices and power modules
Peng Dong received his doctoral degree from Zhejiang University, Hangzhou, China, in 2015. He is currently an Associate Research Fellow with the Microsystem and Terahertz Research Center, Institute of Electronic Engineering, China Academy of Engineering Physics, Mianyang, China. His current research interests are focused on the reliability and defects engineering of power devices
Corresponding author: cuiyingxin@sdu.edu.cn; dongpeng0711@foxmail.com
Received Date: 2025-11-26
Revised Date: 2025-12-28

Available Online: 2026-01-15

Abstract

Abstract

High-temperature reverse bias (HTRB) is one of the most critical reliability for SiC MOSFET, and the termination region is widely regarded as the sensitive area under HTRB stress. Interestingly, through systematically monitoring of the degradation behavior of static electrical parameters under different voltage, this study reveals that the elevated reverse bias (ERB) stress can also induce damage in the gate oxide, which results in the hole trapping and a negative shift of the threshold voltage. Deep level transient spectroscopy (DLTS) measurements were performed and shown that the interface trap density in the gate oxide is promoted after ERB stress. Surprisingly, the reverse leakage current after ERB stress is significantly deteriorated at a gate bias of 0 V, while effectively suppressed by applying a negative gate bias (−5 V), which point to the synergistic effects of channel region on the breakdown voltage. Based on the gate oxide degradations and TCAD simulations, it is elucidated that the trapped positive interface charges in gate oxide cause band bending, leading to the formation of an electron accumulation layer in the channel region at 0 V gate bias and thus resulting in a dominant leakage path. This work reveals the impact and mechanism of the ERB stress induced gate oxide damage on the breakdown voltage and highlights the importance of gate oxide protection, which is of great significance for improving the reliability of SiC MOSFETs in elevated voltage applications.
- elevated reverse bias stress,
- gate oxide degradation,
- synergistic effect,
- interface traps,
- SiC MOSFET.

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