Process integration and structural characterization of three−stacked gate−all−around nanosheet pFETs

Yanpeng Song; Hongxiao Lin; Guangxing Wan; Xiaomeng Liu; Zhenzhen Kong; Junjie Li; Xinhe Wang; Hailing Wang; Zhaoqiang Bai; Xiangsheng Wang; Ying Zhang; Yiwen Zhang; Huilong Zhu; Chao Zhao; Guilei Wang

doi:10.1088/1674-4926/26010046

J. Semicond. > Just Accepted

ARTICLES

Process integration and structural characterization of three−stacked gate−all−around nanosheet pFETs

Yanpeng Song^{1, 2}, Hongxiao Lin^{2, 4}, Guangxing Wan^{2, 4}, Xiaomeng Liu¹, Zhenzhen Kong¹, Junjie Li^{2, 3, 4,}, Xinhe Wang¹, Hailing Wang¹, Zhaoqiang Bai¹, Xiangsheng Wang¹, Ying Zhang¹, Yiwen Zhang¹, Huilong Zhu⁴, Chao Zhao¹ and Guilei Wang^{1, 2, 4,}

+ Author Affiliations

1. Beijing Superstring Academy of Memory Technology, Beijing 100176, China
2. Institute of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100049, China
3. State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
4. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

Author Bio:

Dr. Yanpeng Song obtained her Ph.D. in Physics from the Institute of Physics, Chinese Academy of Sciences in 2020, and completed his postdoctoral research there in 2022. She then joined the Beijing Superstring Institute of Memory. Currently, she serves as an Epitaxy Engineer in the SiGe department, leading core research and development and technology iteration in Si/SiGe superlattice epitaxial growth and in-situ boron/phosphorus (B/P) doping. She has led one National Natural Science Foundation project and published 27 SCI papers in top journals, including Physical Review Letters and Advanced Materials. She also holds 15 national invention patents.

Dr. Junjie Li is a Professorate Senior Engineer at the Institute of Microelectronics, Chinese Academy of Sciences (IMECAS). He earned his Ph.D. from IMECAS in 2021, and previously received his B.S. and M.S. from Wuhan University of Technology and Beihang University. With extensive industry experience, he worked as a Product Manager before joining IMECAS in 2013. His research focuses on nanodevices, key process technologies, mechanisms, and prototype equipment, particularly GAA modeling, SiGe/Si etching, and nanogap release. He has led projects such as the National Natural Science Foundation of China, published numerous papers, and holds multiple patents. He is a recipient of the CAS Technical Support Talent and other honors.

Prof. Guilei Wang received his Ph.D. from the University of Chinese Academy of Sciences in 2016. He served as a researcher at the Institute of Microelectronics, CAS from 2009 to 2021, and became Vice President of the Beijing Superstring Institute of Memory in October 2021. His research focuses on novel semiconductor functional materials, advanced devices, process integration, and Si-based quantum materials. Over the past five years, he has published 66 SCI and conference papers as corresponding author in prestigious journals like Nature Communications, Nano Letters, and IEEE journals, and has edited 4 books.

Corresponding author: Junjie Li, lijunjie@ime.ac.cn; Guilei Wang, Guilei.Wang@bjsamt.org.cn

DOI: 10.1088/1674-4926/26010046CSTR: 32376.14.1674-4926.26010046

Abstract: Recent advancements in strain engineering of Gate−All−Around (GAA) nanosheets (NSs) make the SiGe−cladded Si channel a promising architecture for sub−3 nm logic nodes. In this work, we realize the controllable fabrication of three−stacked hexagonal SiGe−cladded Si NSs via optimized epitaxial growth and selective dry etching processes. Systematic structural characterizations including SEM, TEM and EDS confirm that the epitaxially grown SiGe cladding layer possesses excellent crystallinity and forms sharp, defect−free interfaces with the Si core, which is essential for high quality carrier transport. Beyond empirical process tuning, we further elaborate the underlying mechanism of selective etching kinetics and morphological evolution, and analyze the compressive strain modulation induced by the SiGe cladding structure. This work clarifies the critical process window for scalable three−layer stacking construction, and provides fundamental insights into process optimization, structural regulation and strain engineering for high−yield integration of next−generation GAA NS devices.

Keywords: Gate−all−around (GAA) NSs, SiGe−cladded Si channel, Strain engineering, Process optimization, Selective dry etching, Structural characterization

References

[1]	Bangsaruntip S, Cohen G M, Majumdar A, et al. High performance and highly uniform gate−all−around silicon nanowire MOSFETs with wire size dependent scaling. 2009 IEEE International Electron Devices Meeting (IEDM), 2009: 1
[2]	Barraud S, Previtali B, Vizioz C, et al. 7-levels-stacked nanosheet GAA transistors for high performance computing. 2020 IEEE Symposium on VLSI Technology, 2020: 1
[3]	Lauer I, Loubet N, Kim S D, et al. Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance. 2015 Symposium on VLSI Technology (VLSI Technology), 2015: T140
[4]	Liu M. 1.1 unleashing the future of innovation. 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021: 9
[5]	Loubet N, Hook T, Montanini P, et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. 2017 Symposium on VLSI Technology, 2017: T230
[6]	Mii Y J. Semiconductor innovations, from device to system. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022: 276
[7]	Guo D, Karve G, Tsutsui G, et al. FINFET technology featuring high mobility SiGe channel for 10nm and beyond. 2016 IEEE Symposium on VLSI Technology, 2016: 1
[8]	Tsutsui G, Bao R Q, Lim K Y, et al. Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT. 2016 IEEE International Electron Devices Meeting (IEDM), 2017: 17.4. 1
[9]	Li Y, Cheng X H, Zhao F, et al. Fabrication of high-mobility Si_0.7Ge_0.3 Channel FinFET for optimization of device electrical performance. ECS J Solid State Sci Technol, 2021, 10(7): 075001 doi: 10.1149/2162-8777/ac0f12
[10]	Li Y L, Cheng X H, Zhong Z Y, et al. Key process technologies for stacked double Si_0.7Ge_0.3 Channel nanowires fabrication. ECS J Solid State Sci Technol, 2020, 9(6): 064009 doi: 10.1149/2162-8777/aba67a
[11]	Chu C L, Wu K, Luo G L, et al. Stacked Ge-nanosheet GAAFETs fabricated by Ge/Si multilayer epitaxy. IEEE Electron Device Lett, 2018, 39(8): 1133 doi: 10.1109/LED.2018.2850366
[12]	Mochizuki S, Kumar S, Greene A, et al. SiGe channel for scaled gate-all-around nanosheet pFET transistor for advanced logic applications. 2025 IEEE International Electron Devices Meeting (IEDM), 2026: 1
[13]	Chen Y R, Liu Y C, Lin H C, et al. Fabrication and performance of highly stacked GeSi nanowire field effect transistors. Commun Eng, 2023, 2: 77 doi: 10.1038/s44172-023-00126-8
[14]	Mochizuki S, Colombeau B, Zhang J, et al. Structural and electrical demonstration of SiGe cladded channel for PMOS stacked nanosheet gate-all-around devices. 2020 IEEE Symposium on VLSI Technology, 2020: 1
[15]	Xu H Q, Yao J X, Yang Z Z, et al. Physical insights of Si-core-SiGe-shell gate-all-around nanosheet pFET for 3 nm technology node. IEEE Trans Electron Devices, 2023, 70(6): 3365 doi: 10.1109/TED.2023.3268156
[16]	Wan G X, Wang G L, Zhu H L. Hetero-epitaxy and self-adaptive stressor based on freestanding fin for the 10 nm node and beyond. Chin Phys Lett, 2017, 34(7): 078502 doi: 10.1088/0256-307X/34/7/078502
[17]	Song Y P, Wan G X, et al. Morphological and strain engineering of SiGe cladded channels for stacked nanowire transistors. Appl Phys Lett, 2025, 126(12): 121602 doi: 10.1063/5.0243463
[18]	Borel S, Arvet C, Bilde J, et al. Control of selectivity between SiGe and Si in isotropic etching processes. Jpn J Appl Phys, 2004, 43(6S): 3964 doi: 10.1143/JJAP.43.3964
[19]	Tu C T, Huang Y S, Lu F L, et al. First Vertically Stacked Tensily Strained Ge_0.98Si_0.02 nGAAFETs with No Parasitic Channel and L_G = 40 nm Featuring Record I_ON = 48 μA at V_OV = V_DS = 0.5V and Record G_m, max(μS/μm)/SSSAT(mV/dec) = 8.3 at V_DS = 0.5V. 2019 IEEE International Electron Devices Meeting (IEDM), 2020: 29.3. 1
[20]	Chen Y R, Zhao Z F, Tu C T, et al. I_ON enhancement of Ge_0.98Si_0.02 nanowire nFETs by high-κ dielectrics. IEEE Electron Device Lett, 2022, 43(10): 1601 doi: 10.1109/LED.2022.3201972
[21]	Liu Y C, Tu C T, Tsai C E, et al. First highly stacked Ge_0.95Si_0.05 nGAAFETs with record I_ON = 110 μA (4100 μA/μm) at V_OV = V_DS = 0.5 V and high G_m, _max = 340 μS (13000 μS/μm) at V_DS = 0.5 V by wet etching, 2021 Symposium on VLSI Technology, 2021: 1.
[22]	Liu Y C, Tu C T, Tsai C E, et al. Highly stacked GeSi nanosheets and nanowires by low-temperature epitaxy and wet etching. IEEE Trans Electron Devices, 2021, 68(12): 6599 doi: 10.1109/TED.2021.3110838
[23]	Loubet N, Kormann T, Chabanne G, et al. Selective etching of Si_1−xGe_x versus Si with gaseous HCl for the formation of advanced CMOS devices. Thin Solid Films, 2008, 517(1): 93 doi: 10.1016/j.tsf.2008.08.081
[24]	Destefanis V, Hartmann J M, Hopstaken M, et al. Low-thermal surface preparation, HCl etch and Si/SiGe selective epitaxy on (1 1 0) silicon surfaces. Semicond Sci Technol, 2008, 23(10): 105018 doi: 10.1088/0268-1242/23/10/105018
[25]	Mertens H, Ritzenthaler R, Hikavyy A, et al. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates. 2016 IEEE Symposium on VLSI Technology, 2016: 1
[26]	Tsai Y H, Wang M M. Fundamental study on the selective etching of SiGe and Si in ClF₃ gas for nanosheet gate-all-around transistor manufacturing: A first principle study. J Vac Sci Technol B, 2022, 40: 013201
[27]	Kong Z Z, Lin H X, Wang H L, et al. Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM. J Semicond, 2023, 44(12): 124101 doi: 10.1088/1674-4926/44/12/124101
[28]	Loubet N, Kal S, Alix C, et al. A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around NanoSheet devices. 2019 IEEE International Electron Devices Meeting (IEDM), 2020: 11.4. 1
[29]	Holländer B, Buca D, Mantl S, et al. Wet chemical etching of Si, Si_1–xGe_x, and Ge in HF: H2O2: CH3COOH. J Electrochem Soc, 2010, 157(6): H643 doi: 10.1149/1.3382944
[30]	Kil Y H, Yang J H, Kang S, et al. Selective chemical wet etching of Si_0.8Ge_0.2/Si multilayer. JSTS J Semicond Technol Sci, 2013, 13(6): 668 doi: 10.5573/JSTS.2013.13.6.668
[31]	Kolahdouz M, Maresca L, Ghandi R, et al. Kinetic model of SiGe selective epitaxial growth using RPCVD technique. J Electrochem Soc, 2011, 158(4): H457 doi: 10.1149/1.3548113
[32]	Zhao Y, Iwase T, Satake M, et al. Formation mechanism of a rounded SiGe-etch-front in an isotropic dry SiGe etch process for gate-all-around (GAA)-FETs. 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2021: 1
[33]	Kumar A, Lee W H, Wang Y L. Optimizing the isotropic etching nature and etch profile of Si, Ge and Si_0.8Ge_0.2 by controlling CF₄ atmosphere with Ar and O₂ additives in ICP. IEEE Trans Semicond Manuf, 2021, 34(2): 177 doi: 10.1109/TSM.2021.3057100
[34]	Li J J, Wang W W, Li Y L, et al. Study of selective isotropic etching Si_1–xGe_x in process of nanowire transistors. J Mater Sci: Mater Electron, 2020, 31(1): 134 doi: 10.1007/s10854-019-02269-x
[35]	Xia L R, Yang C R, Li J J, et al. Study of loading effect of cavity etching process for the inner spacer module in gate-all-around transistor manufacturing. J Micro/Nanopattern Mats Metro, 2025, 24(2): 023601
[36]	Yang L, Junjie L, Cinan W, et al. Dry Selective Etching of Si_0.7Ge_0.3 for Horizontal GAA Inner Spacer Module, Chin J Vac Sci Technol, 2023, 43(5): 396
[37]	Li J, Reboh S, Chao R, et al. Nanobeam diffraction and geometric phase analysis for strain measurements in Si/SiGe nanosheet structures. Microanal, 2016, 22(S3): 1528
[38]	Du Y, Wang G L, Miao Y H, et al. Strain modulation of selectively and/or globally grown Ge layers. Nanomaterials, 2021, 11(6): 1421 doi: 10.3390/nano11061421
[39]	Zhang Y H, Chai C C, Fan Q Y, et al. Mechanical and electronic properties of Si Ge alloy in Cmmm structure. Chin J Phys, 2016, 54(2): 298 doi: 10.1016/j.cjph.2016.04.016
[40]	Mochizuki S, Bhuiyan M, Zhou H, et al. Stacked gate-all-around nanosheet pFET with highly compressive strained Si_1-xGe_x channel. 2020 IEEE International Electron Devices Meeting (IEDM), 2020: 2.3. 1

Fig. 2. Cross−sectional SEM images of the failed NSs induced by the anisotropic etching process. (a−d) Unformed NSs, (e−f) Broken NWs. The width of NSs in Figure e is 7.4 and 14.9 nm, and the width of NSs in Figure f is 20.4 and 12.1nm, respectively.

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Fig. 3. Cross−sectional SEM images of the failed NSs induced by the SiGe selective etching. (a−c) Broken NSs by over etching.

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Fig. 4. Key process steps in the formation of stacked Si NSs. (a−c) Anisotropic etching of SiGe/Si multilayers (HBr/O₂), resulting in vertically aligned dumbbell−shaped NSs. (d−f) Subsequent isotropic selective etching of SiGe (CF₄/O₂/He), showing the released Si nanostructures.

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Fig. 1. (Color online) Integration process flow with the three−stacked SiGe cladded Si NSs channel devices.

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Fig. 5. (Color online) Effect of etch time on isotropic etching with CF₄/O₂/He. (a−d) Cross−sectional SEM profiles. (e−f) Quantification of lateral etch depth and etch rate versus time.

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Fig. 6. Cross−sectional SEM images of a three−stacked SiGe−cladded Si NSs with two different channel sizes. (a) Narrow channel (d ~ 25 nm). (b) Wide channel (d ~ 50 nm).

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Fig. 7. (Color online) Cross−sectional SEM images of three−stacked Si/SiGe NSs fabricated by different selective etching processes, with in−situ dimensional labels for each layer. (a-c) All subgraphs have a scale bar of 200 nm. These samples are used for statistical analysis of etching uniformity, dimensional controllability and process yield.

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Fig. 8. (Color online) (a) Cross−sectional TEM images of a three−stacked SiGe cladding structure on Si NSs. (b−d) Magnified TEM micrographs of the SiGe−cladded Si NSs clearly resolve the individual layers of HfO₂, Si, and SiGe. (e−h) EDS elemental mappings of the region corresponding to Si, Ge, O, and Hf.

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Fig. 9. (Color online) Cross−section TEM images of the Si epilayer of (a) Substrate Si layer, (b) Bottom Si layer, (c) Middle Si layer (d) Top Si layer. (e−h) The electron diffraction patterns obtained for different regions.

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Fig. 10. (Color online) (a) TCAD−simulated 3D structure of the three−stacked SiGe−cladded Si NS GAA pMOSFET. (b) Simulated I_d−V_g characteristics at linear (V_ds = −0.05 V) and saturation (V_ds = −1 V) biases.

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Table 1. Summary of key parameters for reported stacked−channel pFET architectures.

Parameter		Si stacked NS[5] (Experimental data)	SiGe stacked NWs[35] (Experimental data)	GeSn stacked NSs [36] (Experimental data)	Ge stacked NSs[11] (Experimental data)	SiGe stacked NWs[17] (Experimental data)	SiGe stacked NWs[17] (Experimental data)	SiGe stacked NWs[17] (TCAD simulation data)	SiGe stacked NWs[16] (TCAD simulation data)
W_NS or D_NW (nm)		~15	30	5	90	15	15	15	15
Gate length (nm)	12		650	60	80	100	500	30	30
Normalization method	N/A		Perimeter of NWs	Footprint of NWs	Footprint of NSs	an effective device width of 80 nm for a single fin	an effective device width of 80 nm for a single fin	Perimeter of NSs	Perimeter of NSs
I_on(μA/μm)	N/A		550	1850	1650	56	19.4	1333	2100
I_on/I_off	~10⁶		~10⁶	~10⁴	~10⁴	~10³	~10³	~10⁴	~10⁴
SS (mV/dec)	85		66	77	130	71.5	68.9	75	65
V_D(V)/V_G(V)	−0.7/−1.2		−1.2/−1.5	−0.5/−2.0	−1.0/−1.0	−0.8/−0.8	−0.8/−0.8	−0.8/−0.8	−0.8/−0.8

DownLoad: CSV

Table 2. Key simulated electrical parameters of SiGe−cladded Si NS−channel pMOSFETs with varying Ge fractions. All devices have a gate length (L_g) of 80 nm.

Parameter	Si_0.95Ge_0.05	Si_0.90Ge_0.10	Si_0.85Ge_0.15
L_g(nm)	80	80	80
I_on(μA/μm) & V_d = V_g = −1 V	547	552	596
I_off(μA/μm) & V_d = −1 V, V_g = 0 V	1.30 × 10⁻⁵	3.81 × 10⁻⁵	7.26 × 10⁻⁵
I_on/I_off	4.2 × 10⁷	1.4 × 10⁷	0.82 × 10⁷
SS_lin(mV/dec)	64.0	64.0	64.5
SS_sat(mV/dec)	77.5	76.4	76.9
Vt_lin(V) & Id_lin = 1e−7×W/L	−0.48	−0.44	−0.42
Vt_sat(V) & Id_sat = 1e−7×W/L	−0.46	−0.42	−0.40
DIBL	21.05	21.05	21.05

DownLoad: CSV

[1]	Bangsaruntip S, Cohen G M, Majumdar A, et al. High performance and highly uniform gate−all−around silicon nanowire MOSFETs with wire size dependent scaling. 2009 IEEE International Electron Devices Meeting (IEDM), 2009: 1
[2]	Barraud S, Previtali B, Vizioz C, et al. 7-levels-stacked nanosheet GAA transistors for high performance computing. 2020 IEEE Symposium on VLSI Technology, 2020: 1
[3]	Lauer I, Loubet N, Kim S D, et al. Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance. 2015 Symposium on VLSI Technology (VLSI Technology), 2015: T140
[4]	Liu M. 1.1 unleashing the future of innovation. 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021: 9
[5]	Loubet N, Hook T, Montanini P, et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. 2017 Symposium on VLSI Technology, 2017: T230
[6]	Mii Y J. Semiconductor innovations, from device to system. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022: 276
[7]	Guo D, Karve G, Tsutsui G, et al. FINFET technology featuring high mobility SiGe channel for 10nm and beyond. 2016 IEEE Symposium on VLSI Technology, 2016: 1
[8]	Tsutsui G, Bao R Q, Lim K Y, et al. Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT. 2016 IEEE International Electron Devices Meeting (IEDM), 2017: 17.4. 1
[9]	Li Y, Cheng X H, Zhao F, et al. Fabrication of high-mobility Si_0.7Ge_0.3 Channel FinFET for optimization of device electrical performance. ECS J Solid State Sci Technol, 2021, 10(7): 075001 doi: 10.1149/2162-8777/ac0f12
[10]	Li Y L, Cheng X H, Zhong Z Y, et al. Key process technologies for stacked double Si_0.7Ge_0.3 Channel nanowires fabrication. ECS J Solid State Sci Technol, 2020, 9(6): 064009 doi: 10.1149/2162-8777/aba67a
[11]	Chu C L, Wu K, Luo G L, et al. Stacked Ge-nanosheet GAAFETs fabricated by Ge/Si multilayer epitaxy. IEEE Electron Device Lett, 2018, 39(8): 1133 doi: 10.1109/LED.2018.2850366
[12]	Mochizuki S, Kumar S, Greene A, et al. SiGe channel for scaled gate-all-around nanosheet pFET transistor for advanced logic applications. 2025 IEEE International Electron Devices Meeting (IEDM), 2026: 1
[13]	Chen Y R, Liu Y C, Lin H C, et al. Fabrication and performance of highly stacked GeSi nanowire field effect transistors. Commun Eng, 2023, 2: 77 doi: 10.1038/s44172-023-00126-8
[14]	Mochizuki S, Colombeau B, Zhang J, et al. Structural and electrical demonstration of SiGe cladded channel for PMOS stacked nanosheet gate-all-around devices. 2020 IEEE Symposium on VLSI Technology, 2020: 1
[15]	Xu H Q, Yao J X, Yang Z Z, et al. Physical insights of Si-core-SiGe-shell gate-all-around nanosheet pFET for 3 nm technology node. IEEE Trans Electron Devices, 2023, 70(6): 3365 doi: 10.1109/TED.2023.3268156
[16]	Wan G X, Wang G L, Zhu H L. Hetero-epitaxy and self-adaptive stressor based on freestanding fin for the 10 nm node and beyond. Chin Phys Lett, 2017, 34(7): 078502 doi: 10.1088/0256-307X/34/7/078502
[17]	Song Y P, Wan G X, et al. Morphological and strain engineering of SiGe cladded channels for stacked nanowire transistors. Appl Phys Lett, 2025, 126(12): 121602 doi: 10.1063/5.0243463
[18]	Borel S, Arvet C, Bilde J, et al. Control of selectivity between SiGe and Si in isotropic etching processes. Jpn J Appl Phys, 2004, 43(6S): 3964 doi: 10.1143/JJAP.43.3964
[19]	Tu C T, Huang Y S, Lu F L, et al. First Vertically Stacked Tensily Strained Ge_0.98Si_0.02 nGAAFETs with No Parasitic Channel and L_G = 40 nm Featuring Record I_ON = 48 μA at V_OV = V_DS = 0.5V and Record G_m, max(μS/μm)/SSSAT(mV/dec) = 8.3 at V_DS = 0.5V. 2019 IEEE International Electron Devices Meeting (IEDM), 2020: 29.3. 1
[20]	Chen Y R, Zhao Z F, Tu C T, et al. I_ON enhancement of Ge_0.98Si_0.02 nanowire nFETs by high-κ dielectrics. IEEE Electron Device Lett, 2022, 43(10): 1601 doi: 10.1109/LED.2022.3201972
[21]	Liu Y C, Tu C T, Tsai C E, et al. First highly stacked Ge_0.95Si_0.05 nGAAFETs with record I_ON = 110 μA (4100 μA/μm) at V_OV = V_DS = 0.5 V and high G_m, _max = 340 μS (13000 μS/μm) at V_DS = 0.5 V by wet etching, 2021 Symposium on VLSI Technology, 2021: 1.
[22]	Liu Y C, Tu C T, Tsai C E, et al. Highly stacked GeSi nanosheets and nanowires by low-temperature epitaxy and wet etching. IEEE Trans Electron Devices, 2021, 68(12): 6599 doi: 10.1109/TED.2021.3110838
[23]	Loubet N, Kormann T, Chabanne G, et al. Selective etching of Si_1−xGe_x versus Si with gaseous HCl for the formation of advanced CMOS devices. Thin Solid Films, 2008, 517(1): 93 doi: 10.1016/j.tsf.2008.08.081
[24]	Destefanis V, Hartmann J M, Hopstaken M, et al. Low-thermal surface preparation, HCl etch and Si/SiGe selective epitaxy on (1 1 0) silicon surfaces. Semicond Sci Technol, 2008, 23(10): 105018 doi: 10.1088/0268-1242/23/10/105018
[25]	Mertens H, Ritzenthaler R, Hikavyy A, et al. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates. 2016 IEEE Symposium on VLSI Technology, 2016: 1
[26]	Tsai Y H, Wang M M. Fundamental study on the selective etching of SiGe and Si in ClF₃ gas for nanosheet gate-all-around transistor manufacturing: A first principle study. J Vac Sci Technol B, 2022, 40: 013201
[27]	Kong Z Z, Lin H X, Wang H L, et al. Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM. J Semicond, 2023, 44(12): 124101 doi: 10.1088/1674-4926/44/12/124101
[28]	Loubet N, Kal S, Alix C, et al. A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around NanoSheet devices. 2019 IEEE International Electron Devices Meeting (IEDM), 2020: 11.4. 1
[29]	Holländer B, Buca D, Mantl S, et al. Wet chemical etching of Si, Si_1–xGe_x, and Ge in HF: H2O2: CH3COOH. J Electrochem Soc, 2010, 157(6): H643 doi: 10.1149/1.3382944
[30]	Kil Y H, Yang J H, Kang S, et al. Selective chemical wet etching of Si_0.8Ge_0.2/Si multilayer. JSTS J Semicond Technol Sci, 2013, 13(6): 668 doi: 10.5573/JSTS.2013.13.6.668
[31]	Kolahdouz M, Maresca L, Ghandi R, et al. Kinetic model of SiGe selective epitaxial growth using RPCVD technique. J Electrochem Soc, 2011, 158(4): H457 doi: 10.1149/1.3548113
[32]	Zhao Y, Iwase T, Satake M, et al. Formation mechanism of a rounded SiGe-etch-front in an isotropic dry SiGe etch process for gate-all-around (GAA)-FETs. 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2021: 1
[33]	Kumar A, Lee W H, Wang Y L. Optimizing the isotropic etching nature and etch profile of Si, Ge and Si_0.8Ge_0.2 by controlling CF₄ atmosphere with Ar and O₂ additives in ICP. IEEE Trans Semicond Manuf, 2021, 34(2): 177 doi: 10.1109/TSM.2021.3057100
[34]	Li J J, Wang W W, Li Y L, et al. Study of selective isotropic etching Si_1–xGe_x in process of nanowire transistors. J Mater Sci: Mater Electron, 2020, 31(1): 134 doi: 10.1007/s10854-019-02269-x
[35]	Xia L R, Yang C R, Li J J, et al. Study of loading effect of cavity etching process for the inner spacer module in gate-all-around transistor manufacturing. J Micro/Nanopattern Mats Metro, 2025, 24(2): 023601
[36]	Yang L, Junjie L, Cinan W, et al. Dry Selective Etching of Si_0.7Ge_0.3 for Horizontal GAA Inner Spacer Module, Chin J Vac Sci Technol, 2023, 43(5): 396
[37]	Li J, Reboh S, Chao R, et al. Nanobeam diffraction and geometric phase analysis for strain measurements in Si/SiGe nanosheet structures. Microanal, 2016, 22(S3): 1528
[38]	Du Y, Wang G L, Miao Y H, et al. Strain modulation of selectively and/or globally grown Ge layers. Nanomaterials, 2021, 11(6): 1421 doi: 10.3390/nano11061421
[39]	Zhang Y H, Chai C C, Fan Q Y, et al. Mechanical and electronic properties of Si Ge alloy in Cmmm structure. Chin J Phys, 2016, 54(2): 298 doi: 10.1016/j.cjph.2016.04.016
[40]	Mochizuki S, Bhuiyan M, Zhou H, et al. Stacked gate-all-around nanosheet pFET with highly compressive strained Si_1-xGe_x channel. 2020 IEEE International Electron Devices Meeting (IEDM), 2020: 2.3. 1

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Received: 31 July 2026 Revised: 18 August 2026 Online: Accepted Manuscript: 10 September 2026

Article Navigation > Journal of Semiconductors > 2026 > Accepted Manuscript

Yanpeng Song, Hongxiao Lin, Guangxing Wan, Xiaomeng Liu, Zhenzhen Kong, Junjie Li, Xinhe Wang, Hailing Wang, Zhaoqiang Bai, Xiangsheng Wang, Ying Zhang, Yiwen Zhang, Huilong Zhu, Chao Zhao, Guilei Wang. Process integration and structural characterization of three−stacked gate−all−around nanosheet pFETs[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26010046 ****Y P Song, H X Lin, G X Wan, X M Liu, Z Z Kong, J J Li, X H Wang, H L Wang, Z Q Bai, X S Wang, Y Zhang, Y W Zhang, H L Zhu, C Zhao, and G L Wang, Process integration and structural characterization of three−stacked gate−all−around nanosheet pFETs[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/26010046

Citation:

Y P Song, H X Lin, G X Wan, X M Liu, Z Z Kong, J J Li, X H Wang, H L Wang, Z Q Bai, X S Wang, Y Zhang, Y W Zhang, H L Zhu, C Zhao, and G L Wang, Process integration and structural characterization of three−stacked gate−all−around nanosheet pFETs[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/26010046

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Process integration and structural characterization of three−stacked gate−all−around nanosheet pFETs

DOI: 10.1088/1674-4926/26010046

CSTR: 32376.14.1674-4926.26010046

1.
Beijing Superstring Academy of Memory Technology, Beijing 100176, China
2.
Institute of Integrated Circuits, University of Chinese Academy of Sciences, Beijing 100049, China
3.
State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
4.
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

More Information

Dr. Yanpeng Song obtained her Ph.D. in Physics from the Institute of Physics, Chinese Academy of Sciences in 2020, and completed his postdoctoral research there in 2022. She then joined the Beijing Superstring Institute of Memory. Currently, she serves as an Epitaxy Engineer in the SiGe department, leading core research and development and technology iteration in Si/SiGe superlattice epitaxial growth and in-situ boron/phosphorus (B/P) doping. She has led one National Natural Science Foundation project and published 27 SCI papers in top journals, including Physical Review Letters and Advanced Materials. She also holds 15 national invention patents
Dr. Junjie Li is a Professorate Senior Engineer at the Institute of Microelectronics, Chinese Academy of Sciences (IMECAS). He earned his Ph.D. from IMECAS in 2021, and previously received his B.S. and M.S. from Wuhan University of Technology and Beihang University. With extensive industry experience, he worked as a Product Manager before joining IMECAS in 2013. His research focuses on nanodevices, key process technologies, mechanisms, and prototype equipment, particularly GAA modeling, SiGe/Si etching, and nanogap release. He has led projects such as the National Natural Science Foundation of China, published numerous papers, and holds multiple patents. He is a recipient of the CAS Technical Support Talent and other honors
Prof. Guilei Wang received his Ph.D. from the University of Chinese Academy of Sciences in 2016. He served as a researcher at the Institute of Microelectronics, CAS from 2009 to 2021, and became Vice President of the Beijing Superstring Institute of Memory in October 2021. His research focuses on novel semiconductor functional materials, advanced devices, process integration, and Si-based quantum materials. Over the past five years, he has published 66 SCI and conference papers as corresponding author in prestigious journals like Nature Communications, Nano Letters, and IEEE journals, and has edited 4 books
Corresponding author: lijunjie@ime.ac.cn; Guilei.Wang@bjsamt.org.cn
Received Date: 2026-07-31
Revised Date: 2026-08-18

Available Online: 2026-09-10

Abstract

Abstract

Recent advancements in strain engineering of Gate−All−Around (GAA) nanosheets (NSs) make the SiGe−cladded Si channel a promising architecture for sub−3 nm logic nodes. In this work, we realize the controllable fabrication of three−stacked hexagonal SiGe−cladded Si NSs via optimized epitaxial growth and selective dry etching processes. Systematic structural characterizations including SEM, TEM and EDS confirm that the epitaxially grown SiGe cladding layer possesses excellent crystallinity and forms sharp, defect−free interfaces with the Si core, which is essential for high quality carrier transport. Beyond empirical process tuning, we further elaborate the underlying mechanism of selective etching kinetics and morphological evolution, and analyze the compressive strain modulation induced by the SiGe cladding structure. This work clarifies the critical process window for scalable three−layer stacking construction, and provides fundamental insights into process optimization, structural regulation and strain engineering for high−yield integration of next−generation GAA NS devices.
- Gate−all−around (GAA) NSs,
- SiGe−cladded Si channel,
- Strain engineering,
- Process optimization,
- Selective dry etching,
- Structural characterization

Supplementary materials to this article can be found online at https://doi.org/10.1088/1674-4926/26010046.

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