Fig. 1.
(Color online) SBD architecture and high-freq leakage.
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Journal of Semiconductors
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2026
> Accepted Manuscript
| Citation: |
Yufeng Ge, Ziqi Xue, Xuanyu Li, Aoxuan Wen, Hongzhi Wu, Pingyi Cai, Xuxu Cheng, Quan Pan. Trends and advanced techniques in high-speed simultaneous bi-directional transceivers for die-to-die interfaces[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26040030
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Y F Ge, Z Q Xue, X Y Li, A X Wen, H Z Wu, P Y Cai, X X Cheng, and Q Pan, Trends and advanced techniques in high-speed simultaneous bi-directional transceivers for die-to-die interfaces[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/26040030
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Trends and advanced techniques in high-speed simultaneous bi-directional transceivers for die-to-die interfaces
DOI: 10.1088/1674-4926/26040030
CSTR: 32376.14.1674-4926.26040030
More Information-
Yufeng Ge received the B.S. and M.S. degrees from Xi’an Jiaotong University (XJTU), Xi’an, China, in 2022 and 2025, respectively. He is currently pursuing the Ph.D. degree at the Southern University of Science and Technology (SUSTech), Shenzhen, China. His current research interests include high-speed SerDes design and memory interface -
Ziqi Xue is currently an undergraduate student in the School of Microelectronics, Southern University of Science and Technology (SUSTech), Shenzhen, China. Her research interests include mixed-signal clocking systems and analog front-ends for high-speed wireline transceivers -
Xuanyu Li is currently an undergraduate student in the School of Microelectronics, Southern University of Science and Technology (SUSTech), Shenzhen, China. His research interests include high-speed wireline receivers and optical receivers -
Aoxuan Wen is currently an undergraduate student in the School of Microelectronics, Southern University of Science and Technology (SUSTech), Shenzhen, China. His research interests include high-speed and mixed-signal integrated circuit design -
Hongzhi Wu (Member, IEEE) received the B.S. degree in communication engineering from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2020, and the Ph.D. degree from the Southern University of Science and Technology (SUSTech), Shenzhen, China, in 2025. His research interests include high-speed wireline transceivers and low-power equalizers -
Pingyi Cai received the B.S. degree from Southern University of Science and Technology, Shenzhen, China, in 2021. He is currently pursuing a Ph.D. degree at the Southern University of Science and Technology, Shenzhen, China. His current research interests focus on high-speed receiver circuit design -
Xuxu Cheng (Graduate Student Member, IEEE) received the B.S. degree from Wuhan University,Wuhan, China, in 2018, and the M.S. degree in electronic and communication engineering from Shanghai Jiao Tong University, Shanghai, China, in 2021. He is currently pursuing the Ph.D. degree with the Southern University of Science and Technology, Shenzhen, China. His current research interests include high-speed transceiver circuit design -
Quan Pan (Senior Member, IEEE) received B.S. degree in electrical engineering (EE) from the University of Science and Technology of China (USTC), Hefei, China, in 2005, and the Ph.D. degree in electronics and computer engineering (ECE) from The Hong Kong University of Science and Technology (HKUST), Hong Kong, China, in 2014. From 2014 to 2018, he was a Senior Staff Engineer at one Silicon Valley start-up company, working on 400-GbE high-speed SerDes. He joined the School of Microelectronics, Southern University of Science and Technology (SUSTech), Shenzhen, China, in 2018, as an Assistant Professor, where he is currently a Full Professor with early promotions. He has contributed more than 90 peer-reviewed articles. His research interests include high-speed optical and wireline circuit design. Dr. Pan received the 2017 Outstanding Young Author Award of IEEE Circuits and System Society. He serves as an Active Reviewer for many international journals, including JSSC, TCAS, TVLSI, JLT, PTL, and JoS - Corresponding author: panq@sustech.edu.cn
- Revised Date: 2026-06-04 Available Online: 2026-06-15
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References
[1] Nishi Y, Poulton J W, Turner W J, et al. A 0.297-pJ/bit 50.4-Gb/s/wire inverter-based short-reach simultaneous bi-directional transceiver for die-to-die interface in 5-nm CMOS. IEEE J Solid State Circuits, 2023, 58(4): 1062 doi: 10.1109/JSSC.2022.3232024[2] Tomita Y, Tamura H, Kibune M, et al. A 20Gb/s bidirectional transceiver using a resistor-transconductor hybrid. 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006: 2102[3] Farjadrad R, Kaviani K, Nguyen D, et al. 11.8 an echo-cancelling front-end for 112Gb/s PAM-4 simultaneous bidirectional signaling in 14nm CMOS. 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021: 194[4] Lee Y, Shim M, Roh S, et al. An 80-Gb/s PAM-4 simultaneous bidirectional transceiver with hybrid adaptation scheme. IEEE Trans Circuits Syst II, 2023, 70(8): 2884 doi: 10.1109/tcsii.2023.3253679[5] Huang Z W, Wang Z F, Ye B Y, et al. 8.4 a 112Gb/S/wire single-ended simultaneous bi-directional transceiver with dynamic equalizer for die-to-die interface in 28nm CMOS. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 140[6] Sun H F, Wei S J, Su Y, et al. A 112Gb/s PAM-4 SBD transceiver with mismatch-compensated 2 × VDD hybrid and two-step echo canceller in 28nm CMOS. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 146[7] Kim K, Lee Y, Na D, et al. 8.8 a 0.292pJ/b 56Gb/s/wire capacitively driven simultaneous bidirectional transceiver with PVT/Mismatch tracking for XSR and D2D interfaces in 28nm cmos. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 148[8] Cheng X X, Wu H Z, Li Z H, et al. 8.9 a 72Gb/s/pin single-ended simultaneous bi-directional transceiver with C-peaking leakage cancellation and dual-loop hybrid impedance calibration for chiplet interfaces. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 150[9] Lee S, Yun J, Kim S. A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS. 2022 IEEE International Solid-State Circuits Conference (ISSCC), 2022: 454[10] Nishi Y, Poulton J W, Turner W J, et al. A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. IEEE J Solid State Circuits, 2024, 59(4): 1146 doi: 10.1109/JSSC.2023.3338478[11] Walter D, Höppner S, Eisenreich H, et al. A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. 2012 IEEE International Solid-State Circuits Conference, 2012: 180[12] Lin M S, Tsai C C, Li S G, et al. 36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025: 586[13] Seong K, Park D, Bae G, et al. A 4nm 32Gb/s 8Tb/s/mm die-to-die chiplet using NRZ single-ended transceiver with equalization schemes and training techniques. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023: 114[14] Yuan C, Naguib A, Shekhar S. On the design of low-power hybrids for full duplex simultaneous bidirectional signaling links. IEEE Trans Circuits Syst I, 2020, 67(4): 1413 doi: 10.1109/tcsi.2019.2962359[15] Fan Y-H, Kumar A, Iwai T, et al. A 32-Gb/s simultaneous bidirectional source-synchronous transceiver with adaptive echo cancellation techniques. IEEE J Solid State Circuits, 2020, 55(2): 439 doi: 10.1109/JSSC.2019.2956369 -
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