| Citation: |
Zhou Liren, Luo Lei, Ye Fan, Xu Jun, Ren Junyan. A 12-bit 100 MS/s pipelined ADC with digital background calibration[J]. Journal of Semiconductors, 2009, 30(11): 115007. doi: 10.1088/1674-4926/30/11/115007
****
Zhou L R, Luo L, Ye F, Xu J, Ren J Y. A 12-bit 100 MS/s pipelined ADC with digital background calibration[J]. J. Semicond., 2009, 30(11): 115007. doi: 10.1088/1674-4926/30/11/115007.
|
A 12-bit 100 MS/s pipelined ADC with digital background calibration
DOI: 10.1088/1674-4926/30/11/115007
-
Abstract
This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter (MDAC) while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18 μm CMOS process, occupies an active area of 2.3 × 1.6 mm2, and consumes 205 mW at 1.8 V.-
Keywords:
- pipelined analog-to-digital converter
-
References
-
Proportional views
DownLoad: