J. Semicond. > 2009, Volume 30 > Issue 2 > 025006

SEMICONDUCTOR INTEGRATED CIRCUITS

A 13-bit, 8 MSample/s pipeline A/D converter

Guo Dandan, Li Fule, Zhang Chun and Wang Zhihua

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DOI: 10.1088/1674-4926/30/2/025006

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Abstract: A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-and-hold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-mm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW (including I/O drivers) when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm, including I/O pads.

Key words: analog-to-digital converter

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    Received: 18 August 2015 Revised: 09 October 2008 Online: Published: 01 February 2009

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      Guo Dandan, Li Fule, Zhang Chun, Wang Zhihua. A 13-bit, 8 MSample/s pipeline A/D converter[J]. Journal of Semiconductors, 2009, 30(2): 025006. doi: 10.1088/1674-4926/30/2/025006 ****Guo Dandan, Li F L, Zhang C, Wang Z H. A 13-bit, 8 MSample/s pipeline A/D converter[J]. J. Semicond., 2009, 30(2): 025006. doi: 10.1088/1674-4926/30/2/025006.
      Citation:
      Guo Dandan, Li Fule, Zhang Chun, Wang Zhihua. A 13-bit, 8 MSample/s pipeline A/D converter[J]. Journal of Semiconductors, 2009, 30(2): 025006. doi: 10.1088/1674-4926/30/2/025006 ****
      Guo Dandan, Li F L, Zhang C, Wang Z H. A 13-bit, 8 MSample/s pipeline A/D converter[J]. J. Semicond., 2009, 30(2): 025006. doi: 10.1088/1674-4926/30/2/025006.

      A 13-bit, 8 MSample/s pipeline A/D converter

      DOI: 10.1088/1674-4926/30/2/025006
      • Received Date: 2015-08-18
      • Accepted Date: 2008-07-30
      • Revised Date: 2008-10-09
      • Published Date: 2009-02-16

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