A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners

Wang Keping; Wang Zhigong; Zhou Jianzheng; Lei Xuemei; Zhou Mingzhu

doi:10.1088/1674-4926/30/3/035002

J. Semicond. > 2009, Volume 30 > Issue 3 > 035002

SEMICONDUCTOR INTEGRATED CIRCUITS

A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners

Wang Keping, Wang Zhigong, Zhou Jianzheng, Lei Xuemei and Zhou Mingzhu

+ Author Affiliations

DOI: 10.1088/1674-4926/30/3/035002

Abstract: A broadband CMOS intermediate frequency (IF) variable-gain amplifier (VGA) for DRM/DAB tuners is presented. The VGA comprises two cascaded stages: one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18 μm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of –10 to 18 dB. It can operate in the frequency range of 30–700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is –3.9 dBm.

Key words: VGA, noise-canceling, linear-in-dB, CMOS

1	A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18 μm CMOS Bao Kuan, Fan Xiangning, Li Wei, Zhang Li, Wang Zhigong, et al. Journal of Semiconductors, 2012, 33(1): 015003. doi: 10.1088/1674-4926/33/1/015003
2	A 10-Gb/s inductor-less variable gain amplifier with a linear-in-dB characteristic and DC-offset cancellation Liu Chang, Yan Yuepeng, Goh Wang-Ling, Xiong Yongzhong, Zhang Lijun, et al. Journal of Semiconductors, 2012, 33(8): 085003. doi: 10.1088/1674-4926/33/8/085003
3	A highly linear fully integrated CMOS power amplifier with an analog predistortion technique Jin Boshi, Li Lewei, Wu Qun, Yang Guohui, Zhang Kuang, et al. Journal of Semiconductors, 2011, 32(5): 054006. doi: 10.1088/1674-4926/32/5/054006
4	CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers Lei Qianqian, Chen Zhiming, Shi Yin, Chu Xiaojie, Gong Zheng, et al. Journal of Semiconductors, 2011, 32(10): 105008. doi: 10.1088/1674-4926/32/10/105008
5	A high-performance low-power CMOS AGC for GPS application Lei Qianqian, Xu Qiming, Chen Zhiming, Shi Yin, Lin Min, et al. Journal of Semiconductors, 2010, 31(2): 025005. doi: 10.1088/1674-4926/31/2/025005
6	A novel 2.95–3.65 GHz CMOS LC-VCO using tuning curve compensation Xiao Shimao, Ma Chengyan, Ye Tianchun Journal of Semiconductors, 2009, 30(10): 105001. doi: 10.1088/1674-4926/30/10/105001
7	A CMOS Dynamic Comparator for Pipelined ADCs with Improved Speed/Power Ratio Liu Ke, Yang Haigang Journal of Semiconductors, 2008, 29(1): 75-81.
8	Transient Characteristic Analysis of a Double-Gate Dual-Strained-Channel SOI CMOS Sun Liwei, Gao Yong, Yang Yuan, Liu Jing Journal of Semiconductors, 2008, 29(8): 1566-1569.
9	Analysis and Modeling of Broadband CMOS Monolithic Balun up to Millimeter-Wave Frequencies Xia Jun, Wang Zhigong, Wu Xiushan, Li Wei Journal of Semiconductors, 2008, 29(3): 467-472.
10	A Novel CMOS Current Mode Bandgap Reference Xing Xinpeng, Li Dongmei, Wang Zhihua Journal of Semiconductors, 2008, 29(7): 1249-1253.
11	Sensitivity Design for a CMOS Optoelectronic Integrated Circuit Receiver Zhu Haobo, Mao Luhong, Yu Changliang, Ma Liyuan Chinese Journal of Semiconductors , 2007, 28(5): 676-680.
12	Low-Power CMOS IC for Function Electrical Stimulation of Nerves Li Wenyuan, Wang Zhigong, 张震宇 Chinese Journal of Semiconductors , 2007, 28(3): 393-397.
13	Design and Implementation of an Optoelectronic Integrated Receiver in Standard CMOS Process Yu Changliang, Mao Luhong, Song Ruiliang, Zhu Haobo, Wang Rui, et al. Chinese Journal of Semiconductors , 2007, 28(8): 1198-1203.
14	Concept and Simulation of a Novel Pre-Equalized CMOS Optoelectronic Integrated Receiver Yu Changliang, Mao Luhong, Zhu Haobo, Song Ruiliang, Chen Mingyi, et al. Chinese Journal of Semiconductors , 2007, 28(6): 951-957.
15	A High Speed,12-Channel Parallel,Monolithic IntegratedCMOS OEIC Receiver Zhu Haobo, Mao Luhong, Yu Changliang, Chen Hongda, Tang Jun, et al. Chinese Journal of Semiconductors , 2007, 28(9): 1341-1345.
16	Single-Stage Wide-Range CMOS VGA with Temperature Compensation and Linear-in-dB Gain Control Yun Tinghua, Yin Li, Wu Jianhui, Shi Longxing Chinese Journal of Semiconductors , 2007, 28(4): 518-525.
17	Characterization and Modeling for 0.13μm RF MOSFETs Chi Yusong, Huang Fengyi, Wu Zhongjie, Zhang Shaoyong, Kong Xiaoming, et al. Chinese Journal of Semiconductors , 2006, 27(2): 373-376.
18	A Model of the Temperature Dependence of the Fall Time ofa TF SOI CMOS Inverter with EM NMOST and AMPMOST Assemblies at 27～300℃ Zhang Haipeng, Wei Tongli, Feng Yaolan, Wang Qin, Zhang Zhengfan, et al. Chinese Journal of Semiconductors , 2006, 27(S1): 36-39.
19	A Novel Offset-Cancellation Technique for Low Voltage CMOS Differential Amplifiers Han Shuguang, Chi Baoyong, Wang Zhihua Chinese Journal of Semiconductors , 2006, 27(5): 778-782.
20	Characterization and Modeling of Finite-Ground Coplanar Waveguides in 0.13μm CMOS Chen Xu, Wang Zhigong Chinese Journal of Semiconductors , 2006, 27(6): 982-987.

Search

GET CITATION

Wang Keping, Wang Zhigong, Zhou Jianzheng, Lei Xuemei, Zhou Mingzhu. A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners[J]. Journal of Semiconductors, 2009, 30(3): 035002. doi: 10.1088/1674-4926/30/3/035002

Wang K P, Wang Z G, Zhou J Z, Lei X M, Zhou M Z. A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners[J]. J. Semicond., 2009, 30(3): 035002. doi: 10.1088/1674-4926/30/3/035002.

Export: BibTex EndNote

Article Metrics

Article views: 4750 Times PDF downloads: 2241 Times Cited by: 0 Times

History

Received: 18 August 2015 Revised: 13 October 2008 Online: Published: 01 March 2009

A broadband CMOS intermediate frequency (IF) variable-gain amplifier (VGA) for DRM/DAB tuners is presented. The VGA comprises two cascaded stages: one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18 μm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of –10 to 18 dB. It can operate in the frequency range of 30–700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is –3.9 dBm.

A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners

DOI: 10.1088/1674-4926/30/3/035002

Abstract

References

Proportional views

Catalog

A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners

DOI: 10.1088/1674-4926/30/3/035002

Abstract

References

Proportional views

Catalog

Export File

Citation

Format

Content