A novel radiation hardened by design latch

Huang Zhengfeng; Liang Huaguo

doi:10.1088/1674-4926/30/3/035007

J. Semicond. > 2009, Volume 30 > Issue 3 > 035007

SEMICONDUCTOR INTEGRATED CIRCUITS

A novel radiation hardened by design latch

Huang Zhengfeng and Liang Huaguo

+ Author Affiliations

DOI: 10.1088/1674-4926/30/3/035007

Abstract: Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-event-upset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.

Key words: soft error, single event upset, radiation hardened by design latch

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Received: 18 August 2015 Revised: 30 July 2008 Online: Published: 01 March 2009

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-event-upset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.

A novel radiation hardened by design latch

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