SEMICONDUCTOR INTEGRATED CIRCUITS
Gao Zhuo, Yang Zongren, Zhao Ying, Yang Yi, Zhang Lu, Huang Lingyi and Hu Weiwu
Abstract: This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300×500 μm2. With the novel half rate period calibration clock data recovery (CDR) circuit, the receiver consumes 52 mW power. The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE).
Key words: serial link, receiver, CDR, equalizer
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Received: 18 August 2015 Revised: 01 November 2008 Online: Published: 01 April 2009
| Citation: |
Gao Zhuo, Yang Zongren, Zhao Ying, Yang Yi, Zhang Lu, Huang Lingyi, Hu Weiwu. A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner[J]. Journal of Semiconductors, 2009, 30(4): 045008. doi: 10.1088/1674-4926/30/4/045008
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Gao Z, Yang Z R, Zhao Y, Yang Y, Zhang L, Huang L Y, Hu W W. A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner[J]. J. Semicond., 2009, 30(4): 045008. doi: 10.1088/1674-4926/30/4/045008.
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