J. Semicond. > 2009, Volume 30 > Issue 5 > 055010

SEMICONDUCTOR INTEGRATED CIRCUITS

A 16-bit cascaded sigma–delta pipeline A/D converter

Li Liang, Li Ruzhang, Yu Zhou, Zhang Jiabin and Zhang Jun’an

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DOI: 10.1088/1674-4926/30/5/055010

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Abstract: A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma–delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.

Key words: multi-bit sigma–delta ADC

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    Received: 18 August 2015 Revised: Online: Published: 01 May 2009

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      Li Liang, Li Ruzhang, Yu Zhou, Zhang Jiabin, Zhang Jun’an. A 16-bit cascaded sigma–delta pipeline A/D converter[J]. Journal of Semiconductors, 2009, 30(5): 055010. doi: 10.1088/1674-4926/30/5/055010 ****Li L, Li R Z, Yu Z, Zhang J B, Zhang J. A 16-bit cascaded sigma–delta pipeline A/D converter[J]. J. Semicond., 2009, 30(5): 055010. doi: 10.1088/1674-4926/30/5/055010.
      Citation:
      Li Liang, Li Ruzhang, Yu Zhou, Zhang Jiabin, Zhang Jun’an. A 16-bit cascaded sigma–delta pipeline A/D converter[J]. Journal of Semiconductors, 2009, 30(5): 055010. doi: 10.1088/1674-4926/30/5/055010 ****
      Li L, Li R Z, Yu Z, Zhang J B, Zhang J. A 16-bit cascaded sigma–delta pipeline A/D converter[J]. J. Semicond., 2009, 30(5): 055010. doi: 10.1088/1674-4926/30/5/055010.

      A 16-bit cascaded sigma–delta pipeline A/D converter

      DOI: 10.1088/1674-4926/30/5/055010
      • Received Date: 2015-08-18

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