Using the first-principles approach based upon the density functional theory (DFT), we have studied the electronic structure of wurtzite ZnO systems doped with C at different sites. When Zn is substituted by C, the system turns from a direct band gap semiconductor into an indirect band gap semiconductor, and donor levels are formed. When O is substituted by C, acceptor levels are formed near the top of the valence band, and thus a p-type transformation of the system is achieved. When the two kinds of substitution coexist, the acceptor levels are compensated for all cases, which is unfavorable for the p-type transformation of the system.

A two-probe system of the heterojunction formed by an (8, 0) carbon nanotube (CNT) and an (8, 0) silicon carbide nanotube (SiCNT) was established based on its optimized structure. By using a method combining nonequilibrium Green's function (NEGF) with density functional theory (DFT), the transport properties of the het-erojunction were investigated. Our study reveals that the highest occupied molecular orbital (HOMO) has a higher electron density on the CNT section and the lowest unoccupied molecular orbital (LUMO) mainly concentrates on the interface and the SiCNT section. The positive and negative threshold voltages are +1.8 and -2.2 V, respectively.

Porous silicon (PS) samples were fabricated by pulse current etching using different times. The down-ward uniformity and optical properties of the PS layers have been investigated using reflectance spectroscopy, photo-luminescence spectroscopy, and scanning electron microscopy (SEM). The relationship between the refractive index and the optical thickness of PS samples and the etching depth has been analyzed in detail. As the etching depth increases, the average refractive index decreases, indicating that the porosity becomes higher, and the formation rate of the optical thickness decreases. Meanwhile, the reflectance spectra exhibit less intense interference oscillations, which mean the uniformity and interface smoothness of the PS layers become worse. In addition, the intensity of PL emission spectra is slightly increased.

ZnO films and ZnO:Cu diluted magnetic semiconductor films were prepared by radio frequency mag-netron sputtering on Si (111) substrates, with targets of ZnO and Zn0.99Cu0.01, respectively. The plasma emission spectra were analyzed by using a grating monochromator during sputtering. The X-ray photoelectron spectroscopy measurements indicate the existence of Znidefect in the films, and the valence state of Cu is 1+. The X-ray diffrac-tion measurements indicate that the thin films have a hexagonal wurtzite structure and have a preferred orientation along thec-axis. The vibrating sample magnetometer measurements indicate that the sample is ferromagnetic at room temperature, and the origin of the magnetic behavior of the samples is discussed.

CdTe nanocrystalline thin films have been prepared on glass, Si and Al2O3 substrates by radio-frequency magnetron sputtering at liquid nitrogen temperature. The crystal structure and morphology of the films were charac-terized by X-ray diffraction (XRD) and field-emission scanning electron microscopy (FESEM). The XRD examina-tions revealed that CdTe films on glass and Si had a better crystal quality and higher preferential orientation along the (111) plane than the Al2O3. FESEM observations revealed a continuous and dense morphology of CdTe films on glass and Si substrates. Optical properties of nanocrystalline CdTe films deposited on glass substrates for different deposited times were studied.

In the experiment, acid leaching under an ultrasonic field (20 kHz, 80 W) was used to remove Al, Fe, and Ti impurities in metallurgical grade silicon (MG-Si). The effects of the acid leaching process parameters, including the particle size of silicon, the acid type (HCl, HNO3, HF) and the leaching time on the purification of MG-Si were investigated. The results show that HCl leaching, an initial size of 0.1 mm for the silicon particles, and 8 h of leaching time are the optimum parameters to purify MG-Si. The acid leaching process under an ultrasonic field is more effective than the acid leaching under magnetic stirring, the mechanism of which is preliminarily discussed.

For a further improvement of the noise performance in AlGaN/GaN HEMTs, reducing the relatively high gate leakage current is a key issue. In this paper, an experiment was carried out to demonstrate that one method during the device fabrication process can lower the noise. Two samples were treated differently after gate recess etching: one sample was annealed before metal deposition and the other sample was left as it is. From a comparison of their Ig–Vg characteristics, a conclusion could be drawn that the annealing can effectively reduce the gate leakage current. The etching plasma-induced damage removal or reduction after annealing is considered to be the main factor responsible for it. Evidence is given to prove that annealing can increase the Schottky barrier height. A noise model was used to verify that the annealing of the gate recess before the metal deposition is really effective to improve the noise performance of AlGaN/GaN HEMTs.

An AlGaN/GaN recessed-gate MOSHEMT was fabricated on a sapphire substrate. The device, which has a gate length of 1 μm and a source-drain distance of 4 μm, exhibits a maximum drain current density of 684 mA/mm at Vgs = 4 V with an extrinsic transconductance of 219 mS/mm. This is 24.3% higher than the transconductance of conventional AlGaN/GaN HEMTs. The cut-off frequency and the maximum frequency of oscillation are 9.2 GHz and 14.1 GHz, respectively. Furthermore, the gate leakage current is two orders of magnitude lower than for the conventional Schottky contact device.

A novel MEMS inertial sensor with enhanced sensing capacitors is developed. The designed fabricated process of the sensor is a deep RIE process, which can increase the mass of the seismic to reduce the mechanical noise, and the designed capacitance sensing method is changing the capacitance area, which can reduce the air damping between the sensing capacitor plates and reduce the requirement for the DRIE process precision, and reduce the electronic noise by increasing the sensing voltage to improve the resolution. The design and simulation are also verified by using the FEM tool ANSYS. The simulated results show that the transverse sensitivity of the sensor is approximately equal to zero. Finally, the fabricated process based on silicon–glass bonding and the preliminary test results of the device for testing grid capacitors and the novel inertial sensor are presented. The testing quality factor of the testing device based on the slide-film damping effect is 514, which shows that the enhanced capacitors can reduce mechanical noise. The preliminary testing result of the sensitivity is 0.492 pf/g.

This paper presents the modeling, fabrication, and measurement of a capacitive membrane MEMS microwave power sensor. The sensor measures microwave power coupled from coplanar waveguide (CPW) transmission lines by a MEMS membrane and then converts it into a DC voltage output by using thermopiles. Since the fabrication process is fully compatible with the GaAs monolithic microwave integrated circuit (MMIC) process, this sensor could be conveniently embedded into MMIC. From the measured DC voltage output and S-parameters, the average sensitivity in the X-band is 225.43 V/mW, while the reflection loss is below –14 dB. The MEMS microwave power sensor has good linearity with a voltage standing wave ration of less than 1.513 in the whole X-band. In addition, the measurements using amplitude modulation signals prove that the modulation index directly influences the output DC voltage.

Resonant-cavity light-emitting diodes (RCLED) at 650 nm wavelength were grown by metal organic chemical vapor deposition. In order to improve the interface quality and reduce the device voltage, an AlGaInP material system has been chosen to grow the top DBRs. The emission properties of the RCLED were characterized by measuring PL and EL spectra. The average emission power of the device is 0.5 mW at 20 mA and 2.2 V, and its spectrum full width at half maximum is about 10 nm.

A novel symmetrical microwave power sensor based on MEMS technology is presented. In this power sensor, the left section inputs the microwave power, while the right section inputs the DC power. Because of its symmetrical structure, this power sensor provides more accurate microwave power measurement capability without mismatch uncertainty and temperature drift. The loss caused by the microwave signal is simulated in this power sensor. This power sensor is designed and fabricated using GaAs MMIC technology. And it is measured in the frequency range up to 20 GHz with an input power in the 0–80 mW range. Over the 80 mW dynamic range, the sensitivity can achieve about 0.2 mV/mW. The difference between the input power in the two sections is below 0.1% for an equal output voltage. In short, the key aspect of this power sensor is that the microwave power measurement is replaced with a DC power measurement.

We numerically investigate four-wave-mixing (FWM) based multichannel wavelength conversion for amplitude-modulated signals, phase-modulated signals, together with mixed amplitude and phase modulated signals. This paper also discusses the influence of stimulated Brillouin scattering (SBS) effects on high-efficiency FWM-based wavelength conversion applications. Our simulation results show that DPSK signals are more suitable for FWM-based multichannel wavelength conversion because the OOK signals will suffer from the inevitable data-pattern-dependent pump depletion. In future applications, when the modulation format is partially upgraded from OOK to DPSK, the influence of OOK signals on the updated DPSK signals must be considered when using multi-channel wavelength conversion. This influence becomes severe with the increase of OOK channel number. It can be concluded that DPSK signals are more appropriate for both transmission and multichannel wavelength conversion, especially in long haul and high bit-rate system.

The elevated and room temperature annealing behavior of radiation damage in JFET-input operational amplifiers (op-amps) were investigated. High- and low-dose-rate irradiation results show that one of the JFET-input op-amps studied in this paper exhibits enhanced low-dose-rate sensitivity and the other shows time-dependent ef-fect. The offset voltage of both op-amps increases during long-term annealing at room temperature. However, the offset voltage decreases at elevated temperature. The dramatic difference in annealing behavior at room and elevated temperatures indicates the migration behavior of radiation-induced species at elevated and room temperatures. This provides useful information to understand the degradation and annealing mechanisms in JFET-input op-amps under total ionizing radiation. Moreover, the annealing of oxide trapped charges should be taken into consideration, when using elevated temperature methods to evaluate low-dose-rate damage.

Based on the Gummel–Poon model of BJT, the change of the DC bias as a function of the AC input signal in RF linear power amplifiers is theoretically derived, so that the linearity of different DC bias circuits can be interpreted and compared. According to the analysis results, a quantitative adaptive DC bias circuit is proposed, which can improve the linearity and efficiency. From the simulation and test results, we draw conclusions on how to improve the design of linear power amplifier.

This paper describes a divide-by-two injection-locked frequency divider (ILFD) for frequency synthesizers as used in multiband orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18 μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz (6.23 to 11.08 GHz) at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38×0.28 mm2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.

We design a digital pre-amplifier which can be directly connected to an electret microphone. The amplifier can convert analog signals into digital signals, has a wide voltage swing and low power consumption, as is required in portable applications. Measurement results show that the dynamic range of the digital pre-amplifier reaches 88 dB, the equivalent input referred noise is 5 Vrms, the typical power consumption is 540 W, and in standby mode the current does not exceed 10 A. Compared with an analog microphone, an electret microphone with digital pre-amplifier offers a better SNR, higher integration, lower power consumption, and higher immunity to system noise.

A low-noise amplifier (LNA) operated at 40 GHz is designed. An improved cascode configuration is proposed and the design of matching networks is presented. Short-circuited coplanar waveguides (CPWs) were used as inductors to achieve a high Q-factor. The circuit was fabricated in a 0.13-μm SiGe BiCMOS technology with a transistor transit frequency fT of 103 GHz. The chip area is 0.21 mm2. The LNA has one cascode stage with a –3 dB bandwidth from 34 to 44 GHz. At 40 GHz, the measured gain is 8.6 dB; the input return loss, S11, is –16.2 dB; and the simulated noise figure is 5 dB. The circuit draws a current of only 3 mA from a 2.5 V supply.

It has been shown that charge pumps (CPs) dominate single-event transient (SET) responses of phase-locked loops (PLLs). Using a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. An analysis of single event transients in PLLs demonstrates that the settling time of the voltage-controlled oscillators (VCOs) control voltage after a single event strike is strongly dependent on the peak control voltage deviation, the SET pulse width, and the settling time constant. And the peak control voltage disturbance decreases with the SET strength or the filter resistance. Furthermore, the analysis in the proposed PLL model is confirmed by simulation results using MATLAB and HSPICE, respectively.

A 1:2 demultiplexer (DEMUX) has been designed and fabricated in SMIC's standard 0.18-μm CMOS technology, based on standard CML logic and current-density-centric design philosophy. For the integrity of the DEMUX and the reliability of the internal operations, a data input buffer and a static latch were adopted. At the same time, the static latch enables the IC to work in a broader data rate range than the dynamic latch. Measurement results show that under a 1.8-V supply voltage, the DEMUX can operate reliably at any data rate in the range of 5–20 Gb/s. The chip size is 875×640 m2 and the power consumption is 144 mW, in which the core circuit has a share of less than 28%.

A 2.4-GHz SiGe HBT power amplifier (PA) with a novel bias current controlling circuit has been realized in IBM 0.35-μm SiGe BiCMOS technology, BiCMOS5PAe. The bias circuit switches the quiescent current to make the PA operate in a high or low power mode. Under a single supply voltage of +3.5 V, the two-stage mode-switchable power amplifier provides a PAE improvement up to 56.7% and 19.2% at an output power of 0 and 20 dBm, respectively, with a reduced quiescent current in the low power mode as compared to only operating the PA in the high power mode. The die size is only 1.32×1.37 mm2.

This paper mainly discusses the analysis and design of a finline single-ended mixer and detector. In the circuit, for the purpose of eliminating high-order resonant modes and improving transition loss, metallic via holes are implemented along the mounting edge of the substrate embedded in the split-block of the WG-finline-microstrip transition. Meanwhile, a Ka band slow-wave and bandstop filter, which represents a reactive termination, is designed for the utilization of idle frequencies and operation frequencies energy. Full-wave analysis is carried out to optimize the input matching network of the mixer and the detector circuit using lumped elements to model the nonlinear diode. The exportedS-matrix of the optimized circuit is used for conversion loss and voltage sensitivity analysis. The lowest measured conversion loss is 3.52 dB at 32.2 GHz; the conversion loss is flat and less than 5.68 dB in the frequency band of 29–34 GHz. The highest measured zero-bias voltage sensitivity is 1450 mV/mW at 38.6 GHz, and the sensitivity is better than 1000 mV/mW in the frequency band of 38–40 GHz.

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma–delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted opera-tional transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG–metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P+/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.

We analyze the failure mechanism of W-plug via electromigration made in a 0.5-μm CMOS SPTM process. Failure occurs at the top or bottom of a W-plug via. We design a series of via chains, whose size ranges from 0.35 to 0.55 μm. The structure for the via electromigration test is a long via chain, and the layer in the via is Ti/TiN/W/TiN. Using a self-heated resistor to raise the temperature of the via chain allows the structure to be stressed at lower current densities, which does not cause significant joule heating in the plugs. This reduces the interaction between the plug and the plug contact resistance and the time-to-failure for the via chain. The lifetime of a W-plug via electromigration is on the order of 3E7 s, i.e., far below the lifetime of metal electromigration. The study on W-plug via electromigraion in this paper is beneficial for wafer level reliability monitoring of the ultra-deep submicron CMOS multilayer metal interconnect process.