J. Semicond. > 2009, Volume 30 > Issue 5 > 055011

SEMICONDUCTOR INTEGRATED CIRCUITS

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

Zhu Xubin, Ni Weining and Shi Yin

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DOI: 10.1088/1674-4926/30/5/055011

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Abstract: A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted opera-tional transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

Key words: CMOS analog integrated circuits sample-and-hold circuit double-side bootstrapped switch gain- boosted operational transconductance amplifier

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    Received: 18 August 2015 Revised: 13 January 2009 Online: Published: 01 May 2009

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      Zhu Xubin, Ni Weining, Shi Yin. A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches[J]. Journal of Semiconductors, 2009, 30(5): 055011. doi: 10.1088/1674-4926/30/5/055011 ****Zhu X B, Ni W N, Shi Y. A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches[J]. J. Semicond., 2009, 30(5): 055011. doi: 10.1088/1674-4926/30/5/055011.
      Citation:
      Zhu Xubin, Ni Weining, Shi Yin. A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches[J]. Journal of Semiconductors, 2009, 30(5): 055011. doi: 10.1088/1674-4926/30/5/055011 ****
      Zhu X B, Ni W N, Shi Y. A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches[J]. J. Semicond., 2009, 30(5): 055011. doi: 10.1088/1674-4926/30/5/055011.

      A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

      DOI: 10.1088/1674-4926/30/5/055011
      • Received Date: 2015-08-18
      • Accepted Date: 2008-10-30
      • Revised Date: 2009-01-13
      • Published Date: 2009-04-20

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