| Citation: |
Shui Guohua, Tang Zhaohuan, Wang Zhikuan, Ou Hongqi, Yang Yonghui, Liu Yong, Wang Xueyi. Design of a high-performance PJFET for the input stage of an integrated operational amplifier[J]. Journal of Semiconductors, 2010, 31(1): 014004. doi: 10.1088/1674-4926/31/1/014004
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Shui G H, Tang Z H, Wang Z K, Ou H Q, Yang Y H, Liu Y, Wang X Y. Design of a high-performance PJFET for the input stage of an integrated operational amplifier[J]. J. Semicond., 2010, 31(1): 014004. doi: 10.1088/1674-4926/31/1/014004.
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Design of a high-performance PJFET for the input stage of an integrated operational amplifier
DOI: 10.1088/1674-4926/31/1/014004
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Abstract
With Shockley's approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier (OPA) was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 μm, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz1/2, and current noise of less than 0.05 pA/Hz1/2. -
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