Citation: |
Li Zhiqun, Zheng Shuangshuang, Hou Ningbing. Design of a high performance CMOS charge pump for phase-locked loop synthesizers[J]. Journal of Semiconductors, 2011, 32(7): 075007. doi: 10.1088/1674-4926/32/7/075007
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Li Z Q, Zheng S S, Hou N B. Design of a high performance CMOS charge pump for phase-locked loop synthesizers[J]. J. Semicond., 2011, 32(7): 075007. doi: 10.1088/1674-4926/32/7/075007.
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Design of a high performance CMOS charge pump for phase-locked loop synthesizers
DOI: 10.1088/1674-4926/32/7/075007
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Abstract
A new high performance charge pump circuit is designed and realized in 0.18 μ m CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range. Furthermore, a method of adding a precharging current source is proposed to increase the initial charge current, which will speed up the settling time of CPPLLs. Test results show that the current mismatching can be less than 0.4% in the output voltage range of 0.4 to 1.7 V, with a charge pump current of 100 μ A and a precharging current of 70 μ A. The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.-
Keywords:
- charge pump
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References
[1] [2] [3] [4] [5] [6] -
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