J. Semicond. > 2012, Volume 33 > Issue 7 > 074005
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SEMICONDUCTOR DEVICES

A low on-resistance SOI LDMOS using a trench gate and a recessed drain

Ge Rui, Luo Xiaorong, Jiang Yongheng, Zhou Kun, Wang Pei, Wang Qi, Wang Yuangang, Zhang Bo and Li Zhaoji

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DOI: 10.1088/1674-4926/33/7/074005

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Abstract: An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (Ron,sp) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and Ron,sp of 0.985 mΩ·cm2 (VGS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, Ron,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same Ron,sp.

Key words: trench gate

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    Received: 20 August 2015 Revised: 19 February 2012 Online: Published: 01 July 2012

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      Article Navigation >  Journal of Semiconductors  > 2012  >  33(7): 074005
      Ge Rui, Luo Xiaorong, Jiang Yongheng, Zhou Kun, Wang Pei, Wang Qi, Wang Yuangang, Zhang Bo, Li Zhaoji. A low on-resistance SOI LDMOS using a trench gate and a recessed drain[J]. Journal of Semiconductors, 2012, 33(7): 074005. doi: 10.1088/1674-4926/33/7/074005 ****Ge R, Luo X R, Jiang Y H, Zhou K, Wang P, Wang Q, Wang Y G, Zhang B, Li Z J. A low on-resistance SOI LDMOS using a trench gate and a recessed drain[J]. J. Semicond., 2012, 33(7): 074005. doi: 10.1088/1674-4926/33/7/074005.
      Citation:
      Ge Rui, Luo Xiaorong, Jiang Yongheng, Zhou Kun, Wang Pei, Wang Qi, Wang Yuangang, Zhang Bo, Li Zhaoji. A low on-resistance SOI LDMOS using a trench gate and a recessed drain[J]. Journal of Semiconductors, 2012, 33(7): 074005. doi: 10.1088/1674-4926/33/7/074005 ****
      Ge R, Luo X R, Jiang Y H, Zhou K, Wang P, Wang Q, Wang Y G, Zhang B, Li Z J. A low on-resistance SOI LDMOS using a trench gate and a recessed drain[J]. J. Semicond., 2012, 33(7): 074005. doi: 10.1088/1674-4926/33/7/074005.
      shu

      A low on-resistance SOI LDMOS using a trench gate and a recessed drain

      DOI: 10.1088/1674-4926/33/7/074005

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • Received Date: 2015-08-20
      • Accepted Date: 2012-01-06
      • Revised Date: 2012-02-19
      • Published Date: 2012-06-27

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