Citation: |
Huang Haiyun, Wang Dejun, Li Wenbo, Xu Yue, Qin Huibin, Hu Yongcai. A simplified compact model of miniaturized cross-shaped CMOS integrated Hall devices[J]. Journal of Semiconductors, 2012, 33(8): 084005. doi: 10.1088/1674-4926/33/8/084005
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Huang H Y, Wang D J, Li W B, Xu Y, Qin H B, Hu Y C. A simplified compact model of miniaturized cross-shaped CMOS integrated Hall devices[J]. J. Semicond., 2012, 33(8): 084005. doi: 10.1088/1674-4926/33/8/084005.
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A simplified compact model of miniaturized cross-shaped CMOS integrated Hall devices
DOI: 10.1088/1674-4926/33/8/084005
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Abstract
A simplified compact model for a miniaturized cross-shaped CMOS integrated Hall device is presented. The model has a simple circuit structure, only consisting of a passive network with eight non-linear resistors and four current-controlled voltage sources. It completely considers the following effects: non-linear conductivity, geometry dependence of sensitivity, temperature drift, lateral diffusion, and junction field effect. The model has been implemented in Verilog-A hardware description language and was successfully performed in a Cadence Spectre simulator. The simulation results are in good accordance with the classic experimental results reported in the literature. -
References
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