1. Introduction

With the development of microelectronics, biopotentials become the key part in investigating activities of organisms to neuroscientists and clinicians. Early in the 1950s, Mountcastle^[1] and Hubel^[2] began the research in single neuron recordings performed with extracellular metal microelectrodes. As research in neuroscience continued, more results demonstrated that single neuron recordings poorly explained activities in organisms, while multi-neuron activities provided the way to read activities of the organism. Multi-neuron recording not only provides a new way to investigate neurological disorders such as Parkinson's disease and epilepsy, but also makes it possible to implement neural prosthetics in the future.

Great efforts have been made to develop the multi-channel neural recording system. Large-scale experimental equipment for neural recording constrained the recording channels. With the development of techniques in microelectrode electrode array fabrication^[3-7] and the application specific integrated circuit (ASIC), the activities of a large number of neurons can be recorded at the same time. Furthermore, wireless telemetry links were used in the recording system^{[8, 9]} to eliminate cable tethering and risks of infection. In addition, to solve the problem of transmission of a large amount of data brought by multi-channel wireless transmission, some research groups have included data compression^[10] and spike sorting^{[11, 12]} in their neural recording systems. All of these progressions provided the possibility of long-term full implantation in the future.

Challenges of designing the multi-channel neural recording systems are related to the characteristics of biopotentials. Most of the neural activities lie in a frequency range of 0.1 Hz to 5 kHz, and the amplitude range is 20 $\mu$V to 5 mV^{[13, 14]}. Since neural signals have large ranges in amplitude and frequency, a neural signal recording system must be designed to take this into account. Further, the design of the neural recording system has to account for the electrode-electrolyte interface generating direct current (DC) offset and the high impendence of the electrode. All of these make it essential to design a neural amplifier with good performance. Moreover, the challenges lie in miniaturization, data transmission, noise, power consumption and biocompatibility for chronic implantation.

In this paper, an 8-channel programmable integrated circuit for neural recording is described. The implementation of this chip makes the features of recording channels, such as gain, cut-off frequency, and address, digitally programmable. The programmability of every channel offers users a flexible way to suit for recording different neural signals and different numbers of simultaneous recording.

2. Overall chip architecture

The architecture of the proposed multi-channel analog front-end neural recording chip is shown in Fig. 1. It incorporates 8 fully differential recording channels, an analog time-division multiplexer (TDM), a SAR ADC, a serial peripheral interface (SPI) and digital control unit. Each recording channel consists of an alternating current-(AC-) coupled fully differential preamplifier with a tunable low cut-off frequency, a programmable gain amplifier (PGA) with eight gain settings to meet gain requirement of the neural recording chip, and a 4-order Bessel SC filter to suppress high frequency noise. The low cut-off frequency and high cut-off frequency can be adjusted by programming the preamplifier and SC filter separately.

The neural signals from each channel after amplification are fed to an 8-to-1 analog TDM. Controlled by the digital signals, the TDM allows all 8 amplification channels to share a 9-bit SAR ADC. The SAR ADC digitizes signals at the maximum sampling rate of 20 kS/s per channel. Communication to the chip is accomplished using an SPI. The clock and controlling words for preamplifier, PGA, TDM and the SAR ADC are generated from the digital control unit. Fully differential design throughout the chip could minimize noises efficiently from common-mode interference and digital circuits.

3. Neural signal conditioning

3.1 Preamplifier

To record the neural signals which have a large range in frequency, an AC-coupled preamplifier with adjustable low cut-off frequency is proposed in this work. Meanwhile, the DC offset at the interface of electrode and electrolyte could be eliminated. The preamplifier is based on operational transconductance amplifier (OTA) and T-capacitor feedback network topology. This circuit was first described in Ref. [15]. The schematic of the preamplifier is demonstrated in Fig. 2(a). Figure 2(b) shows the schematic of $\rm {OTA_1}$, it employs a two-stage amplification structure with Miller compensation.

The midband gain of the preamplifier is determined by the T-capacitor network, which is

$\begin{equation}\label{Apre} {A_{\rm pre}} = \frac{C_{1}}{C_{\rm eq}}, \end{equation}$

(1)

where

$\begin{equation}\label{Ceq} {C_{\rm eq}} = \frac{{{C_2}{C_3}}}{{{C_2} + {C_3} + {C_4}}}. \end{equation}$

(2)

The T-capacitor feedback network topology reduces the value of the input capacitance $C_1$ to one tenth to achieve the same midband gain, compared to the traditional capacitor feedback amplifier, which was described in Ref. [16]. Moreover, it improves the input impedance and minimizes signal attenuation.

PMOS devices M1 and M2 are biased in the subthreshold region as a tunable pseudo resistor^[17] in the feedback loop, as presented in Fig. 2(a). The transistors M1, M2, and the T-capacitor network forms the high-pass pole, which is

$\begin{equation}\label{fhp} f_{\rm HP} = \frac{1}{2\pi R_{\rm eq}{C_{\rm eq}}}, \end{equation}$

(3)

where $R_{\rm eq}$ is the equivalent resistance of transistors M1 and M2, and it is dominated by voltage $V_{\rm res}$. For every channel, $V_{\rm res}$ is produced from a 4-bit current digital-to-analog converter (DAC). DAC output change makes $R_{\rm eq}$ vary in the order of $10^9$-$10^{13}$ $\Omega$ and $f_{\rm HP}$ vary from 0.1 Hz to about 300 Hz.

As the midband gain of the preamplifier is much larger than PGA in the design, the noise of each recording channel is dominated by the preamplifier and the noise generated by PGA could be ignored. %It is important to design a low-noise preamplifier. The noise of preamplifier is contributed to by thermal noise of equivalent resistance $R_{\rm eq}$ and noise of $\rm{OTA_1}$. The noise introduced by $\rm{OTA_1}$ consists of both flicker noise and thermal noise. Using pMOS device as the input transistors and increasing their gates area could decrease the flicker noise effectively. The thermal noise is primarily determined by the input transistors M3 and M4. Getting a high transconductance of input transistors is a common way to reduce the thermal noise of $\rm{OTA_1}$.

3.2 Programmable gain amplifier

A PGA is designed as the second stage for amplification in each recording channel to adapt to the large dynamic range in amplitude of the neural signals. Figure 3(a) presents the schematic of the PGA. The topology of the proposed PGA is a fully differential OTA with a resistor feedback network. A typically two-stage amplifier structure with Miller compensation of $\rm{OTA_2}$ is shown in Fig. 3(b). Eight groups of switches and resistors with different values composed the resistor network. The gain of the PGA is given by

$\begin{equation}\label{Apga} {A_{\rm pga}} = \frac{{R_{\rm s}}}{{{R_i}}}, \end{equation}$

(4)

where $R_i$ is one of the eight values ($R_1, R_2, ..., R_8$) chosen from the resistor network and has values in k$\Omega$ range. The switches in the resistor network are controlled by PGA2-PGA0 from SPI, which makes PGA provide different gain.

3.3 Switched capacitor filter

To reduce the noise and improve the signal-to-noise ratio (SNR) before data convention, a 4th-order Basel SC filter was introduced in the design. The SC filter is based on SC integrator and realized through LC-ladder flow graph simulation methods. The schematic of the 4th-order SC filter is demonstrated in Fig. 4(a). Figure 4(b) presents the schematic of the SC integrator. The high cut-off frequency of SC filter could be changed by adjusting the switching frequency $f_{\rm clk}$.

With the implementation of the 4th-order SC filter, the neural recording channel has introduced the network with 6 low-pass poles and a high-pass pole, so that the recorded neural signals can be highly improved before digitalization.

4. Digitization

4.1 Analog-to-digital converter

In biomedical application, the SAR ADC is widely used according to its low-power and medium sampling rate. A rail-to-rail input fully differential SAR ADC is used here to digitize neural signals out of TDM.

In consideration of the SAR ADC's resolution, the analysis of noise is the main factor. The noise before quantization is introduced by preamplifier, PGA, SC filter, and it is determined by the preamplifier because of its high midband gain. Thus the noise performance is dominated by noise at the input interface. The total noise at the input interface includes the electrode thermal noise, the background thermal noise, and the noise of the preamplifier. For a 1 M$\Omega$ electrode in 5 kHz bandwidth operating at 300 K, the thermal noise is 9.1 $\mu V_{\rm rms}$ according to thermal noise spectral density 4$kTR$, while the preamplifier has a limited input-referred noise around 5 $\mu \rm{V_{rms}}$ in the design. The typical background thermal noise is about 5-10 $\mu \rm{V_{rms}}$^[18]. Therefore, the total input noise is at least 20 $\mu V_{\rm rms}$.

The minimal neural signal after amplification could be recognized by the ADC, that is

$\begin{equation}\label{vi} V_{i(\min )} {A_{\rm ch(min)}} > {v_{\rm Q}}, \end{equation}$

(5)

where $V_{i(\min )}$ is the minimal effective neural signal, it is around 20 $\mu V_{\rm rms}$ according to the total input noise analysis. $A_{\rm ch(min)}$ is the minimal gain of the recording channel when PGA is set to have the minimal gain. In this design, $A_{\rm ch(min)}$ has a value of 52 dB. $v_{\rm Q}$ is the quantization noise of the ADC, which is

$\begin{equation}\label{vq} {v_{\rm Q}} = \frac{{{V_{\rm LSB}}}}{{\sqrt {12} }} = \frac{{2{V_{\rm ref}}}}{{\sqrt {12} \times {2^N}}}, \end{equation}$

(6)

where $V_{\rm ref}$ is the reference voltage of the ADC, and $N$ is ADC's resolution. To satisfy this expression, $N$ is at least 7 bits for $V_{\rm ref}$ set to maximum value. In this design, the resolution of the ADC is set to be 9 bits.

The SAR ADC is based on fully differential dual capacitor arrays topology. The capacitor network served as the DAC, as illustrated in Fig. 5. Adopting split capacitor array described in Ref. [19], the scaling capacitor $C_{\rm s}$ is designed as $\frac{16}{15}C$, where $C$ is the unit capacitor. The capacitor network's size is reduced to one-eighth compared to traditional binary-weighted capacitor network.

The SAR ADC works as follows: first, the capacitor network is discharged at the beginning of each sampling period. Then, the comparators are set to store the output-offset voltage during output-offset storage (OOS) phase. The schematic of the output-offset storage is shown in Fig. 6, the input and output of the 3-stage comparators are connected to $V_{\rm cm}$ during OOS phase, and $V_{\rm cm}$ is set to be the half of the reference voltages $V_{\rm refp}$ and $V_{\rm refn}$, so that the offsets of the comparators are stored in the capacitors. In the next step, the ADC is in sampling phase. The bottom sides of the capacitors are connected to the input voltage $V_{\rm inp}$ (or $V_{\rm inn}$). The sampled charge is stored by the capacitor arrays in this phase. After sampling, the ADC begins to convert. The switches of the capacitor arrays are controlled by the SAR logic module, and the charge stored in the sampling phase redistributed between the capacitors. In this phase, it takes 10 clock cycles to complete the comparison and serial output. In this design, The SAR ADC digitizes signals at a maximum rate of 20 kS/s for each channel.

4.2 SPI and digital control unit

To communicate with other devices, the recording chip incorporates an SPI interface, which is commonly used in commercial devices. The SPI uses 3 signals to communicate: SCLK, SDI, and SDO. The controlling data are serials in from SDI to control the chip operation, and the conversion data are serials out by SDO.

The digital control unit is used to adjust the low cut-off frequency of the preamplifier, the gain of the PGA and the channel of the TDM through SPI. As presented in Fig. 7, the recording channels are programmed in frame $N$, and the digitalized recording results, which are composed of 3-bit data for TDM address and 9-bit data for ADC results, are transited to the host in frame $N+1$.

5. Experiment results

5.1 Benchtop test

The chip was designed and fabricated in 0.18-$\mu$m N-well CMOS 1P6M mix-signal process. The area of the chip is measured to be 2.5 $\times$ 2.5 mm$^2$ with pads. The micrograph and the package of the chip are presented in Fig. 8. The modules and the system are tested and the experiment results are illustrated in the following parts.

5.1.1   Neural amplifiers and filters

The frequency response of the preamplifier is presented in Fig. 9. It achieved a midband gain of 46.8 dB. The high pass frequency $f_{\rm HP}$ is less than 1 Hz and 310 Hz respectively. Figure 10 demonstrates the measured input-referred noise spectral density curve for the preamplifier with $f_{\rm HP}$ set less than 0.1 Hz. Integrating the input-referred noise spectral density curve from 1 Hz to 5 kHz except the 50 Hz point generates an input-referred noise of 3.77 $\mu V_{\rm rms}$.

The measured frequency response of PGA is illustrated in Fig. 11. The gain is measured to be 9 dB-24 dB with different setting of PGA0-PGA2.

Figure 12 presents the frequency response of the SC filter with different clock frequency. The high cut-off frequency is measured to be 5.69 kHz, 8.3 kHz and 10 kHz when clock frequency is 1 MHz, 2 MHz and 4 MHz respectively.

The output of channel 1 is selected with MUX2-MUX0 set to 001. The frequency response of channel 1 is shown in Fig. 13; the measured midband gain of channel 1 is 55 dB with PGA set to have a gain of 4. The low cut-off frequency is 0.85 Hz with $V_{\rm res}$ measured to be 0.64 V.

5.1.2   Analog-to-digital converter

For dynamic performance measurements, a full-scale 4.1479 kHz sinusoidal wave is applied to the SAR ADC. Getting 4096 sample points and applied to fast Fourier transform (FFT) analysis gets the power spectral density curve, as shown in Fig. 14. The signal-to-noise and distortion ratio (SINAD) calculated from this curve is 40.16 dB, corresponding to an effective number of bits (ENOB) of 7.4 with the most significant bit (MSB) as the sign bit. The power consumption of the SAR ADC under a 1.8 V supply is 193 $\mu$W.

5.2 In-vivo test

A customized 16-channel neural recording system is proposed in this work and used in the in-vivo test. The recording system is composed of a microelectrode and 16-channel neural recording printed circuit board (PCB). The microelectrode is manufactured on silicon and it is 6 mm long. The impedance of the 16 recording sites on the microelectrode are measured in phosphate buffer solution (PBS). Every recording site has impedance around 2 M$\Omega$ at 1 kHz. Figure 15 shows the micrograph and the package of the 2 $\times$ 8 microelectrode. The diameter of each recording point is 12 $\mu$m. Spaces between two recording points in the same tetrode group and different tetrode group are 50 $\mu$m and 200 $\mu$m respectively.

A commercial module with an onboard Xilinx field programmable gate array (FPGA) and a universal serial bus (USB) microcontroller is used to configure the neural recording chips and communicate with the PC. A graphic user interface (GUI) is developed with LabVIEW to interact with the neural recording system.

The in-vivo recording experiment was shown in Fig. 16. Adult male Sprague-Dawley rats weighing about 250 g were used for the recording experiment. After being anaesthetized with urethane (1.4 g/kg, 20% solution), the rats were immobilized in a standard stereotaxic frame. A stainless steel bone-screw was inserted into the skull. The electrode connector was grounded to the bone-screw using a surface insulated stainless steel wire. Microelectrode arrays were advanced by a hydraulic microdrive (FHC, Bowdoin, ME, USA) to different brain regions. Anesthesia level was monitored by breathing patterns and eye blink reflex during recording. Neural signals were sampled at 20 kS/s and the digitalized results were transmitted in real time to the PC. One second in-vivo recorded results of 8 different channels from the rat's cortex are shown in Fig. 17. The amplitude of the recorded spikes was up to 920 $\mu$V. The spike at 1.78 s in Fig. 17 demonstrates that all of the 8 recording channels had recorded this spike and it could originate from the same neuron group.

Table 1 demonstrated the detailed experimental characteristics of the fully differential programmable neural recording chip and performance comparison with the previous design in Refs. [20-22]. The work in Ref. [21] demonstrated an analog front-end that didn't include the ADC module. The work in Ref. [22] implemented neural recording and stimulation. All of the features of recording channels could be programmed digitally compared to Refs. [20-22]. Furthermore, our work demonstrated a lower input-referred noise. The architecture of this chip is fully differential compared to Refs. [20, 21].

6. Conclusion

This paper has demonstrated an 8-channel fully differential programmable neural recording chip. The fully differential design all over the chip makes it efficient to reduce common-mode noise and the digital interference. The recording channels have tunable bandwidth and gain, which can be configured to suit recording of different biopotentials. The recording mode is flexible to choose any subset of the recording channels and different sampling rates. The customized 16-channel neural recording system has been successfully tested in the in-vivo experiments. In our future work, the neural recording chip will incorporate data compression function and wireless telemetry to transmit large amounts of streaming data wirelessly.