1. Introduction

According to microwave theory, the size of the antenna is close to the electromagnetic (EM) wavelength. Hence, it is possible to integrate an antenna on-chip when the wavelength operation of the antenna is in the millimeter (mm) scale. On-chip antennas have many advantages. First, it is difficult to connect the off-chip antenna with an on-chip RF system at the mm-waveband. Whether using bonding wire or the flip-chip technique, the insertion loss is not negligible. Moreover, packaging an mm-wave system with an on-chip antenna is usually easier than packaging an mm-wave system with an off-chip antenna since interconnection and chip fixation issues do not exist. This advantage lowers the packaging costs and reduces the package size.

During the last decade, some types of on-chip antenna have been presented, such as Yagi^[3], monopole^[5], and patch antennas^[6]. Compared with other antennas, the patch antenna is the only one that can achieve a one-sided radiation pattern, which is favored in some high directivity applications. Meanwhile, as most of the power is concentrated on one side, the patch antenna has better radiation efficiency and gain performance than other kinds of antenna. Furthermore, there is now a general consensus that the patch antenna is an ideal element for antenna arrays due to the small antenna size and simple feed-line structure. Hence, the implementation of on-chip patch antennas is well worthy of further study.

The distance between the on-chip metal layers in a standard CMOS process is basically less than 20 $\mu$m, which is very thin compared with the usual substrate thickness of patch antennas, and would greatly deteriorate the radiation efficiency and limit the bandwidth of the antenna. Reference [6] presented a 60 GHz on-chip patch antenna with an 800 MHz bandwidth, which is narrow compared with other antenna topologies.

In this paper, we present a wideband on-chip mm-wave patch antenna in 0.18 $\mu$m CMOS. The simulated $S_{11}$ is less than -10 dB over 46-95 GHz, which is well matched with the measured results over the available 40-67 GHz frequency range from our measurement equipment. In the following section, the principles of wideband patch antennas will be discussed. Then, a wideband on-chip patch antenna structure will be investigated. In the last two sections, the experimental results will be given out and some conclusions are drawn.

2. The principles of wideband patch antennas

The patch antenna is not a traditional wideband antenna, and two key techniques are proposed to broaden the antenna's bandwidth: minimizing the $Q$ factor and exciting the high-order radiation modes.

From the single-resonator circuit model of the patch antenna^[1], the relationship between the bandwidth and $Q$ is given by

$\begin{equation} {\rm BW}=\frac{\rm VSWR-1}{Q\sqrt{\rm VSWR}}. \end{equation}$

(1)

The total $Q$ of the antenna is given by

$\begin{equation} \frac{1}{Q}=\frac{1}{Q_{\rm rad}}+\frac{1}{Q_{\rm sw}}+\frac{1}{Q_{\rm di}}+\frac{1}{Q_{\rm cu}}+\frac{1}{Q_{\rm sh}}, \end{equation}$

(2)

where $Q_{\rm rad}$ represents the space-wave radiation, $Q_{\rm sw}$ represents the surface-wave radiation, $Q_{\rm di}$ represents the dielectric loss, $Q_{\rm cu}$ represents the conductor loss, and $Q_{\rm sh}$ represents the power leakage of the substrate. The antenna efficiency is given by

$\begin{equation} \eta=\frac{Q}{Q_{\rm rad}}. \end{equation}$

(3)

So $Q_{\rm rad}$ should be much lower than the other $Q$ factors to increase the radiation efficiency. In other words, one should reduce other kinds of power loss as much as possible.

Surface-wave radiation is uncontrolled and becomes the most unwanted power loss of the antenna since it can deteriorate the radiation pattern of the antenna. The best way to minimize surface-wave radiation is to keep its first-order radiation cutoff frequency higher than the operation frequency band of the antenna. The cutoff frequency of surface-wave radiation is given by^[2]

$\begin{equation} f_{\rm c}=\frac{nc}{4h\sqrt{\varepsilon_{\rm r}-1}}. \end{equation}$

(4)

From Eq. (4), we can see that the cutoff frequency is inversely proportional to the substrate thickness, $h$. If the thickness of the substrate is thin enough, then the term $\frac{1}{Q_{\rm sw}}$ referring to the surface-wave power loss would be negligible.

$Q_{\rm di}$ and $Q_{\rm cu}$ can be described as follows:

$\begin{equation} Q_{\rm di}=\frac{1}{\tan \delta}, \end{equation}$

(5)

$\begin{equation} Q_{\rm cu}=h\sqrt{\pi f \mu_0 \sigma}. \end{equation}$

(6)

The radiation quality factor $Q_{\rm rad}$ has the following form:

$\begin{equation} Q_{\rm rad}=\frac{2\omega \varepsilon_{\rm r}}{hG/l}K, \end{equation}$

(7)

where $G$/$l$ is the conductance per unit length of the radiating aperture, and

$\begin{equation} K=\frac{\iint_{\rm area}|E|^2 {\rm d}A} {\phi_{\rm perimeter}|E|^2{\rm d}l}. \end{equation}$

(8)

Based on the aforementioned analyses, it is clear that under the condition of negligible $\frac{1}{Q_{\rm sw}}$, with the increase in substrate thickness, the radiation efficiency and bandwidth of the antenna will be increased as well. Unfortunately, the distance between the top on-chip metal layer and the bottom on-chip metal layer in a standard CMOS process is not thick enough (usually less than 20 $\mu$m) for millimeter-wave antennas and will badly limit the antenna's efficiency and bandwidth. Reference [7] introduced an 860 GHz on-chip patch antenna with 71%antenna efficiency in a 0.13 $\mu$m CMOS technique. The distance between the patch and the ground was 7.2 $\mu$m. To achieve similar antenna efficiency at 60 GHz, the distance should be set proportionally to be around 100 $\mu$m, which is unrealistic on-chip.

One technique to solve this issue is to use off-chip metal underneath the silicon substrate as the ground shield of the patch antenna. Unlike the oxide layer, bulk silicon is a low resistivity substrate, whose resistivity is only 10 $\Omega$$\cdot$cm. This increases the power leakage of the silicon substrate and cuts $Q_{\rm sh}$ down. Based on Eq. (2), if $Q_{\rm sw}$, $Q_{\rm di}$ and $Q_{\rm cu}$ are negligible, then

$\begin{equation} \frac{1}{Q}=\frac{1}{Q_{\rm rad}}+\frac{1}{Q_{\rm sh}}. \end{equation}$

(9)

The antenna efficiency would be

$\begin{equation} \eta=\frac{Q_{\rm sh}}{Q_{\rm sh}+Q_{\rm rad}}. \end{equation}$

(10)

It is clear that the antenna efficiency $\eta$ is positive relative to $Q_{\rm sh}$. Hence, the low-efficiency drawback can be avoided by using a high-resistivity silicon substrate, whose resistivity is usually higher than 1000 $\Omega$$\cdot$cm.

Another technique to broaden the bandwidth of the patch antenna is to carefully design the dimensions of the patch and make the antenna oscillate at several different frequencies. Consider a rectangular patch with width $W$ and length $L$ over a ground plane with a substrate thickness of $h$. As long as the substrate is electrically thin, then the electric field will be z-directed and the interior modes will be TM$_{\rm mn}$. The oscillation frequency of each mode is given by^[2]

$\begin{equation} f_{\rm mn}=\frac{1}{2\pi \sqrt{\mu}\varepsilon}\sqrt{\left(\frac{m\pi}{W}\right)^2+\left(\frac{n\pi}{L}\right)^2}. \end{equation}$

(11)

The formula shows that if $W$ is close to $L$, then the oscillation frequency of the TM10 mode and TM01 mode would be put close to each other and broaden the antenna's bandwidth. In this work, TM20 is also oscillated by setting $L$ similar to $W/$2. The parameters of $L$ and $W$ will be listed in the next section.

3. On-chip mm-wave patch antenna design

Figure 1 shows a cross section of the main substrate and metal layers in the 0.18 $\mu$m CMOS process. Figure 2 shows the top view of the whole antenna topology. The on-chip metal layers are embedded between insulator layers above the bulk silicon substrate. In this work, the patch and feed line are implemented in the M6 layer. The ground plane for the patch is the off-chip metal layer, and the on-chip ground plane is implemented in the M1 layer. Based on the aforementioned analyses, the thickness of the bulk silicon is set to be 200 $\mu$m using the back grinding process. The other dimensional design parameters of the antenna are listed in Table 1.

According to Eq. (9), the patch size is designed to be $W=$ 980 $\mu$m and $L=$ 680 $\mu$m to excite the TM10, TM01 and TM20 modes. The calculated oscillation frequency of each modes are $f_{10}=$ 44.4 GHz, $f_{01}=$ 63.9 GHz, $f_{20}=$ 88.7 GHz, and the feed point is set to be 150 $\mu$m away from the edge of the patch to tune the input impedance. The input impedance of the patch antenna is given by^[1]

$\begin{equation} R_{\rm i}=R_{\rm e}\sin^2\frac{\pi x}{L}, \quad 0 \leqslant x \leqslant \frac{L}{2}, \end{equation}$

(12)

where $R_{\rm i}$ is the input resistance, $R_{\rm e}$ the input resistance at the edge, and $x$ the distance from the center of the patch.

Figure 3 shows the feed-line model of this work. The feed line of the antenna is microstrip 1, whose ground shield is an off-chip metal layer underneath the bulk silicon. However, on-chip circuits use microstrip 2 with M1 as the conducting ground plane. Even these two microstrip lines have the same 50 $\Omega$ characteristic impedance. The difference between the substrate thickness will cause their signal line width to vary a lot (in this work, 135 $\mu$m versus 10 $\mu$m). For the purpose of minimizing the field discontinuity between these two microstrip lines, an on-chip transition structure is needed. Meanwhile, an off-chip connection structure is used to connect the M1 layer and off-chip ground plane. For practical use, the on-chip ground should be connected to the off-chip ground by a bonding wire or 3D penetration technique. However, at the mm-wave range, without a certain matching technique, these connection structures will reduce the impedance matching of the antenna. As this work is a prototype of wideband on-chip patch antenna design, the bonding wire or the 3D penetration interconnection study is not included in this work. Instead, a minimum impedance interconnection structure is adopted and shown in Fig. 4. The probe station is used as the ground plane of the on-chip antenna. Together, the GSG probe, arm and probe station work as an interconnection structure between the M1 layer and the off-chip ground plane (in this work, the off-chip ground plane is the probe station). The inductance of this whole interconnection structure is determined by the GSG probe, which can be calibrated and canceled during the measurements. The drawback of this interconnection structure is that the GSG probe may have an influence on the radiation pattern of the antenna. To minimize this influence, the GSG pad is set to be 800 $\mu$m away from the antenna by microstrip 2. For the SOC systems, the length of microstrip 2 can be varied to satisfy the system requirements.

The on-chip transition part is realized by a tapered structure. Due to the limits of the standard CMOS process, the tapered angle is set to be 45 degrees. The width $y_3$ is set to be four times the width of microstrip 1, so it can minimize the influence of the on-chip ground plane on microstrip 1. The length of microstrip 1 is set to be 800 $\mu$m to minimize the influence of the on-chip ground plane on the radiation pattern of the antenna.

4. Experimental results

Figure 5 shows the 3D view for HFSS simulation. Two ground pads are connected to the off-chip ground by two strips, whose boundary is set to be perfect-E. To simulate the influence of the probe on the radiation pattern of the antenna, the HFSS port excitation model is also shown in Fig. 5.

The 3D radiation pattern of the antenna at 60 GHz is presented in Fig. 6. According to the simulation results, the maximum gain is -5.55 dBi with a 4%radiation efficiency. Figure 7 shows the simulated radiation patterns in the E-plane ($y$-$z$) and H-plane ($x$-$z$) at 60 GHz. In the E-plane, the maximum radiation occurs in the Theta $=$ -22$^\circ$ direction. The asymmetry is caused by the reflection of the on-chip ground plane.

The simulated and measured $S_{11}$ are shown in Fig. 8. Due to the limits of the measurement equipment, only the 40-67 GHz frequency band $S_{11}$ parameter was tested. Despite this, we can see that the simulated $S_{11}$ and the measured $S_{11}$ match well.

Table 2 summarizes the performance of this on-chip antenna in the standard CMOS process and makes a comparison with the state-of-the-art devices^[3-6].

Compared with the other works listed in Table 2, this antenna achieves the widest bandwidth (61 times larger than Ref. [6]). The simulation antenna efficiency is not as good as other works because of the patch and the feed line's current leakage to the substrate. The antenna efficiency can be greatly improved to around 80%by simulation if the substrate is changed to high resistive silicon.

5. Conclusions

This paper presents a wideband on-chip mm-wave patch antenna in 0.18 $\mu$m CMOS with a low-resistivity silicon substrate (10 $\Omega$$\cdot$cm). The antenna uses the back grinding process to reduce the thickness of the silicon substrate to 200 $\mu$m. Furthermore, this antenna takes the probe station as the ground plane and the advantage of the inner connection of the GSG probe and probe station to connect the on-chip ground plane with the off-chip ground plane (the probe station in this work). Ansoft HFSS is used to simulate the performance of the antenna at 60 GHz. The simulated results show that the on-chip antenna can achieve a maximum gain of -5.55 dBi with 4%radiation efficiency. The simulated $S_{11}$ is less than -10 dB over 46-95 GHz, which is well matched with the measured results over the available 40-67 GHz frequency range from our measurement equipment. Compared with the current state-of-the-art devices, the presented on-chip mm-wave antenna achieves a wider bandwidth.