1. Introduction

Automatic gain control (AGC) is an essential function in modern wireless communication system receivers, since the power received through the wireless channel is unpredictable. Generally the power of the received signal varies with the distance between receivers and transmitters or other environmental conditions. If the forward gain of a receiver is constant, then the amplitude of the base signal will vary with the instable input signal, ultimately leading to a loss of information or to an unacceptable performance of the system. In order to obtain a stable base signal there must be a circuit continuously adjusting the gain of the system to maintain a relative constant base signal. Figure 1 shows an AGC circuit used in a direct down RFID receiver architecture. The control signal of a VGA can be analog or digital, the gain of an analog controlled VGA changes continuously and the gain of a digital VGA, generally called a PGA, changes discretely. There are two ways to realize variable gain of an amplifier. The gain of an open loop amplifier can be described as $G_{\rm ain} =G_{\rm m} R_{\rm out}$, where $R_{\rm out}$ is the output resistance of the amplifier, $G_{\rm m}$ is the equivalent transconductance of the amplifier, so the simple way is to change $R_{\rm out}$ and the other method is to modify $G_{\rm m}$. In Ref. [1] a switch resistor array is used to change the ratio of the feedback resistor and the input resistor to realize a PGA circuit. A PGA based on a simple differential gain amplifier with a negative feedback $G_{\rm m}$ boosted source-degeneration differential pair is presented in Ref. [2]. Many AGC circuits and novel architectures have been proposed in recent years. For example, a novel CMOS feed-forward automatic-gain control (FFAGC) amplifier is presented in Ref. [3]; a PGA circuit introduced in Ref. [4] has a dynamic gain range of 3–66 dB with 1 dB gain steps with a total of 64 steps. In Ref. [5] a low power flexible PGA with a three-stage amplifier for software defined radio systems is presented. An AGC loop uses a PGA whose gain is discretely adjusted by a gain-control block by utilizing the scrambler concept in the digital communication systems is reported in Ref. [6].

In this paper we introduce a compact differential CMOS automatic gain control amplifier based on a Gilbert cell with an active load to achieve a high gain. The architecture of the proposed AGC circuit is shown in Fig. 2, which consists of two VGAs, a peak detector, a loop filter an operational amplifier, a $V$–$I$ converter, two 50 $\Omega$ output buffers, and a band-gap reference with a current source to generate a voltage reference biasing circuit.

2. AGC parameter analysis

2.1 Settling time

For an AGC circuit, settling time is the most important system parameter. It must satisfy the system requirements.

(1) Constant settling time. For most system applications, the settling time of an AGC circuit should be kept relatively constant when the input amplitude varies over a wide dynamic range, it means that the time to adjust the gain is independent of the input amplitude level. Achieving a constant gain settling time permits the AGC loop's bandwidth to be maximized for fast signal acquisition while maintaining stability over all operating conditions. In order to get a constant settling time, the gain control function of the VGA must satisfy the following constraint^[7]: $G(V_{\rm c})=k_{\rm G2} {\rm e}^{k_{\rm G1} V_{\rm c}}$, where $G(V_{\rm c})$ is the gain of the VGA and $k_{\rm G1}$, $k_{\rm G2}$ are constants. We can easily conclude that the gain in decibels (dB) should vary linearly with the control signal. The linear-in-dB control relationship between the gain and the control voltage can be described as 20$\lg G(V_{\rm c})=20k_{\rm G1} V_{\rm c} \lg (k_{\rm G2} e)$. The main factor affecting the linear-in-dB relationship is $k_{\rm G1}$. Generally, it varies slightly with design parameters and process. At the same time the gain linear-in-dB relationship ensures the AGC response continuously.

(2) The relationship between settling time and the received signal. If the RF carrier power changes much slower than the information rate of the base signal, an AGC circuit can be used to provide a signal with a well defined average level to the downstream circuit. If the settling time is described as $t_{\rm set}$ it should satisfy the following inequality: $t_{\rm set} \ll t_1$, where $t_1$ is the time of the RF carrier power changes. It enables the AGC circuit to respond rapidly when the carrier power changes for different environmental conditions. On the other hand, the gain of an AGC loop does not vary with the base signal which modulates the RF carrier. Therefore, the settling time must satisfy $t_{\rm set} \gg T_{\rm base}$ to prevent base signal distortion where $T_{\rm base}$ is the period of the base signal.

2.2 Gain dynamic tuning range

For an AGC circuit, the input and output signal dynamic range can be described as $D_{\rm input} =V_{\rm in, max}/V_{\rm in, min}$, $D_{\rm output} =V_{\rm out, max}/V_{\rm out, min}$ respectively. The compression figure of the signal can be described as:

$C=\frac{D_{\rm input} }{D_{\rm output} }=\frac{V_{\rm in, max }}{V_{\rm in, min}} \frac{V_{\rm out, min}}{V_{\rm out, max} }=\frac{G_{\rm max}}{G_{\rm min}}.$

(1)

From Eq. (1) it can be concluded that the compression figure is the ratio of the max gain and the minimum gain, so a high dynamic gain range of an AGC loop will lead to a high gain compression figure. In theory, with a higher gain compression figure, the output level will be more likely to approach a desired constant; but that will cause over sensitivity.

3. Circuit principle and implementation

The architecture of the AGC circuit depicted in Fig. 2, including two VGAs, a peak detector, a loop filter, a $V$–$I$ converter, and novel band-gap reference with voltage reference biasing circuits are designed.

3.1 Variable gain amplifier schematic

The VGA is used to provide controllable gain stages for an AGC circuit loop. The VGA must provide controllable gain, while maintaining good linearity. This paper uses a typical Gilbert cell with a current-source PMOS load to realize a 0–30 dB gain VGA circuit and the AGC circuit loop applies only a two-stage VGA. The VGA schematic is shown in Fig 3. Differential input voltage signal is described as $V_{\rm in} =V_{\rm in1} -V_{\rm in2}$, $V_{\rm c1}$, $V_{\rm c2}$ is the tail current-source control voltage. Generally $K_{\rm MN1} =K_{\rm MN2} =K_{\rm MN3} =K_{\rm MN4}$, $K_{\rm MN5} =K_{\rm MN6} =K_{\rm MN7} =K_{\rm MN8}$ and $K_{\rm MP1} =K_{\rm MP2}$, where $K=\mu _{\rm n, , p} C_{\rm cox} W/L$ for NOMS and the PMOS transistor. From Fig. 3 it can be seen that the tail currents $I_{\rm s1}$, $I_{\rm s2}$ are controlled by $V_{\rm c1}$, $V_{\rm c2}$ respectively. According to the differential pair theory the differential output can be described as:

$V_{\rm out} =r_{\rm o} (I_{\rm MN5} -I_{\rm MN6} )-r_{\rm o} (I_{\rm MN8} -I_{\rm MN7} ) \\ \approx r_{\rm o} (V_{\rm in1} -V_{\rm in2} )\sqrt K (\sqrt {2I_{\rm s1} } -\sqrt {2I_{\rm s2}}).$

(2)

Therefore the gain of the proposed VGA can be depicted as:

$A_{\rm v} =r_{\rm o} \sqrt K (\sqrt {2I_{\rm s1} } -\sqrt {2I_{\rm s2}}),$

(3)

and the output resistance $r_{\rm o}$ can be described as:

$r_{\rm o} =r_{\rm MP1} \parallel r_{\rm MN5} \parallel r_{\rm MN7} \\ =\frac{1}{\lambda _{\rm p} (I_{\rm MN5} +I_{\rm MN7} )}\parallel \frac{1}{\lambda _{\rm n} I_{\rm MN5} }\parallel \frac{1}{\lambda_{\rm n} I_{\rm MN7} } \\ =\frac{1}{(\lambda _{\rm n} +\lambda _{\rm p})(I_{\rm s1} +I_{\rm s2} )}.$

(4)

The parameter $\lambda$ depends on the channel length. It can be replaced by another parameter $V_{\rm E}$, which can be described as $\lambda =\frac{1}{V_{\rm E}}L$; $V_{\rm E}$ is constant for a certain technology.

Generally, $I_{\rm s1} +I_{\rm s2}$ is constant so it can be seen as $A_{\rm v} \propto (\sqrt {2I_{\rm s1} } -\sqrt {2I_{\rm s2}})$. By making $2I_{\rm s1}$ and $2I_{\rm s2}$ largely different in value, we can get a high-gain amplifier. Similarly if $I_{\rm s1}$ and $I_{\rm s2}$ are equal to each other, we can get an infinitely large attenuation. The high resistance active loads increase the gain without more current as Equation (3) shows and corresponding MOS transistor noise is introduced to the circuit. The resistors R1, R2 between the sources of the input transistors improve the linearity without losing any headroom. It needs an extra common mode feed back circuit, which can stabilize the common output voltage for the proposed VGA, as Figure 3 shows.

3.2 Peak detector circuit

In order to detect the amplitude or the intensity of the output a peak detector or a received signal strength indication (RSSI) circuit is needed^[8]. In the proposed AGC feedback loop a peak detector is adopted to test the strength of the signal. Generally it is difficult to enable a peak detector to work for a wide range of input frequencies. In order to design a peak detector for multi-standard wireless receivers, it is necessary to design a peak detector process in a broader range for input signals. A differential positive peak detector for the proposed AGC is shown in Fig. 4^[9]. Two current mirrors, an appropriate capacitor, and a small current source for discharging the extra current are included in the peak detector with two differential amplifiers. A NOMS transistor forced by a suitable bias voltage on the gate supplies a small current source to form a discharge route. The working process can be described as follows: The current flowing to M2 increases with the input voltage $V_{\rm in}$, but the current through M3, M4, and M5 will not change for $V_{\rm p}$ and does not increase immediately. As a result the current flowing to M6, M7 increases to charge the capacitor until the voltage $V_{\rm p}$ is equal to $V_{\rm in}$. Similarly if $V_{\rm in}$ decreases the capacitor discharges through the current source $I_{\rm e}$ until $V_{\rm p}$ is equal to $V_{\rm in}$. From the above analysis both positive and negative differential input signals are fed to two identical positive peak detectors so a relative higher frequency signal can be processed.

3.3 Exponential voltage to current convertor

In order to achieve a linear dB gain control relationship between the proposed VGA's gain and the control voltage needs an exponential function generator. According to the analysis of settling time there must be an exponential $V$–$I$ convertor in the feedback loop to ensure that the tail current varies with the control voltage for the proposed VGA. In this design, the control circuit schematic is shown in Fig. 5^{[10, 11]}. It is very simple and it can tune the gain of the Gilbert cell linearly from $-20$ to 10 dB, which is described in Ref. [12]. As can be seen in Fig. 5, MP2 operating in the linear region can be seen a resistor, $V_{\rm c}$ is the input control voltage, $I_1$, $I_2$ are the converted current and will be mirrored to the tail current by MN1, MN2. From analysis, the relation between $V_{\rm p}$ and $V_{\rm c}$ can be described approximately as $V_{\rm p} =k_1 V_{\rm c} +k_2 V_{\rm c}^2$, when MP2 operates in the linear region the voltage $V_{\rm sd2}$ can be depicted as

$V_{\rm sd2} =\frac{I_{\rm b}}{2K(k_1 V_{\rm c} +k_2 V_{\rm c}^2 -\left| {V_{\rm TP} } \right|)}+\alpha V_{\rm c},$

(5)

where $K$ is the transconductance parameter, $\alpha$, $k_1$, $k_2$ are proportionality factors. The current $I_2$, $I_1$ flowing MP2 MP1 can be derived as:

$I_2 =K(k_1 V_{\rm c} +k_2 V_{\rm c}^2 -\left| {V_{\rm TP} } \right|)V_{\rm sd2} -\frac{1}{2}V_{\rm sd2}^2 \\ =\frac{I_{\rm b}}{2}-\alpha K\left| {V_{\rm TP} } \right|V_{\rm c} +\alpha k_1 KV_{\rm c}^2 +\cdots,$

(6)

$I_1 =I_{\rm b} -I_2 \\ =\frac{I_{\rm b}}{2}+\alpha K\left| {V_{\rm TP} } \right|V_{\rm c} -\alpha k_1 KV_{\rm c}^2 +\cdots.$

(7)

Equations (6) and (7) contain Taylor's series expansion form when $\alpha$, $k_1$, $k_2$, $K$ are proper. According to the Taylor theory, $I_1$, $I_2$ are approximated exponential functions with $V_{\rm c}$. Figure 6 shows the simulation result of the gain tuning range of the two-stage VGA. It can be seen that the gain can be tuned linearly from 0 to 60 dB when the control voltage is varied from 0.28 to 0.92 V.

4. Simulation and measurement results

The proposed AGC circuit described in Section 3 was fabricated in a UMC 0.18-$\mu$m single-poly six-metal CMOS process. The die photo is shown in Fig. 7. The frequency responses of the two-stage VGA were measured using an Agilent E5062A ENA series network analyzer. Measured frequency responses of the two-stage VGA with gains of –10, 0, 10, 20, 30, 40 and 50 dB gain relate to the open loop control voltage change from 0.3 to 0.9 V are shown in Fig. 8. It can be derived that at every 0.1 V increase of the control voltage there is a corresponding 10 dB rise in gain. The measured –3-dB bandwidth is 2.2 MHz when the gain is 50 dB from Fig. 8. The results verify that the circuit can satisfy the required bandwidth to process the base signal with no more than 1 MHz frequency.

The measurement result shows that the AGC maintains about 900 mV differential output amplitude across a wide range of input signal level, as illustrated in Fig. 9. Measurements demonstrate less than –27-dB (875 to 915 mV) of peak-to-peak output amplitude variation across a 26-dB input amplitude range corresponding to a $V_{\rm in}$ $=$ 10–200 mV$_{\rm p-p}$ differential^[13].

The setup process and setting time of the closed loop AGC circuit were measured using amplitude modulation (AM) sine-wave input signals from a Tektronix AFG 3022B. Output signals were measured using an Agilent DSO9404A oscilloscope and because it does not keep a linear-in-dB relationship between the gain and control voltage in the whole tuning range, the setting time changes slightly with the input power. The $V_{\rm p-p}$ of the AM input signal is 50 mV amplitude with a modulation depth 60% and the modulation frequency is 1 kHz. Figure 10 shows that the circuit needs 100 $\mu$s to set up. The setting time is decided by the charge and discharge time of the peak detector and low pass filter and varies with the parameter $k_{\rm G1}$. Through measurement we found that the setting time changes with the modulation depth, for an RF receiver the proposed modulation depth means how much the received signal power changes are caused by environmental or the other conditions. For a maximum $V_{\rm p-p}$ $=$ 50 mV 50% modulation depth AM input signal the setting time is 80 $\mu$s and so on. The IIP3 and OIP3 were measured using an E4438C signal generator and an R & S FSW frequency spectrum analyzer. Figure 11 shows that the IIP3 and OIP3 results correspond to 0.56 dBm IIP3 and 19 dBm in-band OIP3. Table 1 shows the test results of the AGC and makes some comparisons with other papers.

5. Conclusion

An analog baseband closed loop AGC circuit for an RFID direct down receiver has been presented. The circuit detects the signal strength from a mixer in the RFID receiver system and enables the peak-to-peak output voltage to remain approximately constant about 900 mV. Experimental results demonstrate a gain range from –10 to 50 dB. The setting time of the AGC circuit is 100 $\mu$s for a 50 mV amplitude 60% modulation depth input AM signal. The proper setting time prevents the lowest frequency 40 MHz (with 25 $\mu$s period) base signal distortion sufficiently. The IIP3 and OIP3 are 0.56 dBm and 19 dBm, respectively. The small differences between simulation and measurement results may be caused by fabrication, circuit board printing, and the measurement process itself.