Fig. 1.
All standby leakage paths in the SRAM cell.
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| Citation: |
Qing Dong, Yinyin Lin. SRAM standby leakage decoupling analysis for different leakage reduction techniques[J]. Journal of Semiconductors, 2013, 34(4): 045008. doi: 10.1088/1674-4926/34/4/045008
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Q Dong, Y Y Lin. SRAM standby leakage decoupling analysis for different leakage reduction techniques[J]. J. Semicond., 2013, 34(4): 045008. doi: 10.1088/1674-4926/34/4/045008.
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SRAM standby leakage decoupling analysis for different leakage reduction techniques
DOI: 10.1088/1674-4926/34/4/045008
More Information
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Abstract
SRAM standby leakage reduction plays a pivotal role in minimizing the power consumption of application processors. Generally, four kinds of techniques are often utilized for SRAM standby leakage reduction:Vdd lowering (VDDL), Vss rising (VSSR), BL floating (BLF) and reversing body bias (RBB). In this paper, we comprehensively analyze and compare the reduction effects of these techniques on different kinds of leakage. It is disclosed that the performance of these techniques depends on the leakage composition of the SRAM cell and temperature. This has been verified on a 65 nm SRAM test macro.-
Keywords:
- SRAM,
- standby power,
- leakage reduction
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References
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