J. Semicond. > 2013, Volume 34 > Issue 5 > 054003
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SEMICONDUCTOR DEVICES

Kirk effect and suppression for 20 V planar active-gap LDMOS

Weidong Nie1, 2, , Fayou Yi2 and Zongguang Yu1

+ Author Affiliations

 Corresponding author: Nie Weidong, Email:youdanwd@163.com

DOI: 10.1088/1674-4926/34/5/054003

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Abstract: For 20 V planar active-gap lateral double-diffused MOSFET (LDMOS), the sectional channel is utilized to decrease the electric field in the n-drift region below the poly gate edge in the off-state, compared with the conventional single channel. Then the n-drift concentration can be increased to decrease the Kirk effect, while keeping off-state breakdown voltage Vbd unchanged. Meanwhile the influence of the n-drift concentration and the n-drift length Ldrift (the drain n+ diffusion to gate spacing) which are related to the Kirk effect is discussed. The trade-offs between Rdson·Area, breakdown voltage Vbd and the electrical safe operating area (e-SOA) performance of LDMOS are considered also. Finally the proposed planar active-gap LDMOS devices with varied values of Ldrift are experimentally demonstrated. The experimental results show that the Kirk effect can be greatly suppressed with slight increase in the Rdson·Area parameter.

Key words: planar active-gap LDMOS, sectional channel, n-drift length Ldrift, n-drift concentration, Kirk effect, electrical safe operating area



[1]
Hower P L, Pendharkar S. Short and long-term safe operating area considerations in LDMOS transistors. IEEE Annual International Reliability Physics Symposium Proceedings, 2005: 545
[2]
Podgaynaya A, Pogany D, Gornik E, et al. Enhancement of the electrical safe operating area of integrated DMOS transistors with respect to high-energy short duration pulses. IEEE Trans Electron Devices, 2010, 57(11):3044 doi: 10.1109/TED.2010.2069564
[3]
Shrivastava M, Gossner H, Baghini M S, et al. Part Ⅰ:on the behavior of STI-type DeNMOS device under ESD conditions. IEEE Trans Electron Devices, 2010, 57(9):2235 doi: 10.1109/TED.2010.2055276
[4]
Steighner J B, Yuan J S. The effect of SOA enhancement on device ruggedness under UIS for the LDMOSFET. IEEE Trans Device Mater Reliab, 2011, 11(2):254 doi: 10.1109/TDMR.2011.2121068
[5]
Kinoshita K, Kawaguchi Y, Nakagawa A. A new adaptive Resurf concept for 20 V LDMOS without breakdown voltage degradation at high current. Proceedings of International Symposium on Power Semiconductor Devices and ICs, 1998: 65
[6]
Amerasekera A, Ramaswamy S, Chang M, et al. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations. IEEE Annual International Reliability Physics Symposium Proceedings, 1996: 318
[7]
Ng K, Lynch W. Analysis of the gate-voltage-dependent series resistance of MOSFETs. IEEE Trans Electron Devices, 1986, 33(7):965 doi: 10.1109/T-ED.1986.22602
Fig. 1.  Cross section of (a) proposed S-LDMOS (b) and conventional C-LDMOS.

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Fig. 2.  (a) Potential distribution of S-LDMOS. (b) Potential distribution of C-LDMOS. (c) Vertical electric field along the poly gate edge for both devices. ($L_{\rm gate}$ $=$ 1.0 $\mu$m, $N_{\rm s}$ $=$ 1.0 $\times$ 10$^{17}$ cm$^{-3}$ at $V_{\rm gs}$ $=$ 0 V and $V_{\rm ds}$ $=$ 20 V).

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Fig. 3.  (a) Profiles of net charge concentration. (b) Electric field distributions at 0.1 $\mu$m below the surface in the n-drift region. The devices for different values of n-drift concentration are at 10 V $V_{\rm gs}$ and 1.0 mA/$\mu$m $I_{\rm ds}$ biases.

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Fig. 4.  (a) Distributions of the vertical electron current density along poly gate edge. (b) Lateral electric field profiles at 0.1 $\mu $m below the surface. With $N_{\rm s}$ $=$ 1.0 $\times$ 10$^{17}$ cm$^{-3}$, the devices are at 10 V $V_{\rm gs}$ bias and 0.8 mA/$\mu$m current with $L_{\rm drift}$ of 0.6 $\mu$m, 0.9 $\mu$m and 1.2 $\mu $m, respectively.

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Fig. 5.  (a) Snapback voltage and snapback current versus the n-drift length and concentration. (b) Off-state breakdown voltage $V_{\rm bd}$ and $R_{\rm dson}$$\cdot$Area versus the n-drift length and concentration. Label $a$, $b$, $c$ and $d$ correspond to the surface concentrations of 0.6 $\times$ 10$^{17}$ cm$^{-3}$, 1.0 $\times$ 10$^{17}$ cm$^{-3}$, 1.7 $\times$ 10$^{17}$ cm$^{-3}$ and 2.4 $\times$ 10$^{17}$ cm$^{-3}$, respectively.

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Fig. 6.  Measured $I$–$V$ curves for varied values of n-drift length (the gate width $W$ $=$ 150 $\mu $m).

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Fig. 7.  Experimental results about the trade-offs between $R_{\rm dson}$$\cdot$Area, snapback voltage and snapback current.

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[1]
Hower P L, Pendharkar S. Short and long-term safe operating area considerations in LDMOS transistors. IEEE Annual International Reliability Physics Symposium Proceedings, 2005: 545
[2]
Podgaynaya A, Pogany D, Gornik E, et al. Enhancement of the electrical safe operating area of integrated DMOS transistors with respect to high-energy short duration pulses. IEEE Trans Electron Devices, 2010, 57(11):3044 doi: 10.1109/TED.2010.2069564
[3]
Shrivastava M, Gossner H, Baghini M S, et al. Part Ⅰ:on the behavior of STI-type DeNMOS device under ESD conditions. IEEE Trans Electron Devices, 2010, 57(9):2235 doi: 10.1109/TED.2010.2055276
[4]
Steighner J B, Yuan J S. The effect of SOA enhancement on device ruggedness under UIS for the LDMOSFET. IEEE Trans Device Mater Reliab, 2011, 11(2):254 doi: 10.1109/TDMR.2011.2121068
[5]
Kinoshita K, Kawaguchi Y, Nakagawa A. A new adaptive Resurf concept for 20 V LDMOS without breakdown voltage degradation at high current. Proceedings of International Symposium on Power Semiconductor Devices and ICs, 1998: 65
[6]
Amerasekera A, Ramaswamy S, Chang M, et al. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations. IEEE Annual International Reliability Physics Symposium Proceedings, 1996: 318
[7]
Ng K, Lynch W. Analysis of the gate-voltage-dependent series resistance of MOSFETs. IEEE Trans Electron Devices, 1986, 33(7):965 doi: 10.1109/T-ED.1986.22602

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    Received: 24 September 2012 Revised: 12 November 2012 Online: Published: 01 May 2013

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      Article Navigation >  Journal of Semiconductors  > 2013  >  34(5): 054003
      Weidong Nie, Fayou Yi, Zongguang Yu. Kirk effect and suppression for 20 V planar active-gap LDMOS[J]. Journal of Semiconductors, 2013, 34(5): 054003. doi: 10.1088/1674-4926/34/5/054003 ****W D Nie, F Y Yi, Z G Yu. Kirk effect and suppression for 20 V planar active-gap LDMOS[J]. J. Semicond., 2013, 34(5): 054003. doi: 10.1088/1674-4926/34/5/054003.
      Citation:
      Weidong Nie, Fayou Yi, Zongguang Yu. Kirk effect and suppression for 20 V planar active-gap LDMOS[J]. Journal of Semiconductors, 2013, 34(5): 054003. doi: 10.1088/1674-4926/34/5/054003 ****
      W D Nie, F Y Yi, Z G Yu. Kirk effect and suppression for 20 V planar active-gap LDMOS[J]. J. Semicond., 2013, 34(5): 054003. doi: 10.1088/1674-4926/34/5/054003.
      shu

      Kirk effect and suppression for 20 V planar active-gap LDMOS

      DOI: 10.1088/1674-4926/34/5/054003
      • 1.

        School of Information, Jiangnan University, Wuxi 214122, China

      • 2.

        Wuxi Crystal Source Electronics Co., Ltd., Wuxi 214028, China

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      • Corresponding author: Nie Weidong, Email:youdanwd@163.com
      • Received Date: 2012-09-24
      • Revised Date: 2012-11-12
      • Published Date: 2013-05-01

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