1. Introduction

With the rapid development of integrated circuit (IC) applications such as microprocessors, optical transmission links, and chip-to-chip communications, a transceiver, which is a key component for these applications, has to continually provide high transmission speed with good signal integrity (SI) and low power consumption. In recent years, several high performance wireline communication standards such as PCI express (PCIE)^[1] and universal serial bus (USB) have been developed, where parameters of the transmitter and receiver for the serial link have been specified. The specifications (PCIE 2.1 and USB 3.0) support data rates from 2.5 to 5 Gb/s and even higher speeds in the future, however, higher data rate or a longer cable length will degrade the magnitude. Thus, the transmitter is specified with the large output signal swing (800-1200 mV differential peak to peak voltage swing) and a pre-emphasis option of 3.5 dB and 6 dB to compensate the loss. As a result, large power is consumed at the transmitter. Meanwhile, it means that there is a heavy load on the pre-stage circuit, which makes circuit design difficult and complex. Furthermore, the 8b/10b code specified in the standards provides the odd input bits for the transmitter, making the traditional 2$^{n}$:1 serializer^[2] useless in these applications.

In this paper, a 5 Gb/s serial link transmitter with pre-emphasis for multiple standards is proposed. A current mode (CM) output driver with the reverse scaling technique and bias current filtering (BCF) is implemented. The reverse scaling technique is introduced to save on pre-driver power and mitigate the load of the pre-stage circuit, and the BCF is adopted to suppress the output common mode noise. In order to cooperate with the 8b/10b encoder, a high speed and low power combined serializer with 10 bits input is proposed. The transmitter operates at both 2.5 Gb/s and 5 Gb/s, and the parameters are in full compliance with the PCIE 2.1 and USB 3.0 standard specifications with a significant margin. In the following, Section 2 discusses the typical pre-emphasis driver architectures. In Section 3, the proposed transmitter is described. Finally, the measurement results are shown in Section 4.

2. Pre-emphasis driver architectures

Transmitters usually contain several components, such as data generators and encoders, serializers, output drivers, etc. Among them, the output driver is the most important part of the transmitter, since it is the bottleneck of bandwidth and consumes most of the power of the whole transmitter. The output driver usually employs differential data transmission to improve the immunity and compliance to the noise. Actually, the output driver is a switch bridge driving a differential 100 $\Omega$ load resistor at the receiver. The load resistor also provides optimum line impedance matching of the receiver. Also, to compensate the losses caused by the package and channel, the pre-emphasis technique is usually implemented at the output driver.

There are generally two different architectures used for pre-emphasis output drivers: voltage mode (VM)^[2-4] and current mode (CM)^[5-9]. The equivalent circuit of a 2-tap pre-emphasis VM output driver is shown in Fig. 1(a). The output driver is subdivided into a pull-up branch and a pull-down branch implemented as a PMOS or NMOS switch transistors. Each of the two branches with several slice units is sized to match the transmission line's 50 $\Omega$ impedance. Therefore, the maximum output signal swing is half of the difference between $V_{\rm H}$ and $V_{\rm L}$, and the total current of the driver $I_{\rm t}$ is equal to the current flowing into the load resistor ($I_{\rm Load})$. However, the switches implemented by the MOS transistors have very large size to achieve small impedance, and often combine with the impedance control circuit, which consumes more power and area. The 2-tap pre-emphasis is implemented by assigning some slice units to the main tap and the remaining slice units to the post cursor tap. So the pre-emphasis level ratio is set by the ratio of the slice units' number for the main tap and post cursor tap. The main disadvantage of the VM output driver is that it creates undesired data-dependent supply current (DDSC) fluctuations that increase with larger pre-emphasis level ratio settings. The DDSC fluctuations will generate the local supply noise according to $v_{\rm n, \, ps}$ $=$ $-L$(d$i$/d$t$), which demands the complex supply regulator. Although the recently reported technique^[4] could mitigate this penalty, it needs programmable resistances, which consume additional power and area.

Figure 1(b) presents the simplified schematic of the 2-tap CM pre-emphasis output driver. The main tap data drives the switches of the main driver to switch the current from one leg to the other, and the current $I_{\rm Load}$ produces the correct output signal swing. The inverted data, which is delayed by 1 bit, is sent to the post cursor driver to implement the 2-tap pre-emphasis signal using the current summing technique. Consequently, the pre-emphasis level ratio is set by the ratio of the two tail currents $I_1$ and $I_2$. The 50 $\Omega$ resistors provide the proper single source termination to the transmission line, so the reflection is suppressed. However, the CM output driver dissipates four times the load current ($I_{\rm t}$ $=$ 4$I_{\rm Load})$ compared with the VM architecture when the same maximum output signal is produced. Moreover, the large current of the driver leads to the large capacitance for the input data. This dictates the use of multiple pre-driver stages which will consume more power and limit the bandwidth of the whole output driver.

Table 1 summarizes the VM and CM pre-emphasis output driver used for comparison. It can be deduced that the VM output driver consumes about 1/4 the output driver power of the CM, but it has difficulties in achieving flexible pre-emphasis and swing setting, constant current, and area efficiency. Additionally, the power savings are mitigated by the higher complexity of the impedance control, pre-emphasis setting circuit, and supply regulator. Fundamentally, the CM output driver separates the impedance matching from the switching devices, allowing the flexible current summing technique to implement the pre-emphasis and swing level control. Also, the current source of the CM driver has high output impedance that has less impact on the termination impedance, so it offers better SI performance than that of VM output drivers^[9].

3. Circuit implementation

Figure 2 shows the transmitter architecture. The 10 bit input parallel data is generated by either a parallel pseudo random bit stream (PRBS) generator or an 8b/10b encoder, running at 500 MHz. These data streams are then converted into a 5 Gb/s data stream by the serializer, and finally sent to the load by the output driver with 2-tap pre-emphasis. The data generator and serializer are worked at 1.2 V power supply with a thin-oxide CMOS, while the output driver is powered by 2.5 V supply with a thick-oxide CMOS.

3.1 Serializer

The serializer is used to convert the 10 bit 500 Mb/s parallel data into 5 Gb/s serial main and post cursor tap data for pre-emphasis operation. The traditional high speed serializer^[2] using tree architecture, however, could only convert 2$^{n}$ bit parallel data into a serial data stream. Although another type serializer-shift register (SR) architecture^[10] could handle arbitrary parallel data, the operating speed of this architecture is limited and the power consumption is relatively large.

In order to serialize 10 bit parallel data to a 5 Gb/s data stream with the lowest power, a serializer combined with the SR and tree architecture is implemented. As shown in Fig. 3, a 5:1 SR clocked by both of the half rate clock CLK2 and the select clock SCLK generates an even (Deven) and an odd (Dodd) data stream out of the 10 bit input at the 500 MHz. The relationship of CLK2, CLK10, and SCLK is shown on the right-hand side of Fig. 3. The lowest bit data of the even (or odd) data is first shifted to the output by the MUX, and the highest bit data is shifted at last. The 2:1 MUX at the last stage (the simplest tree architecture, in fact) of the serializer converts the Deven and Dodd into the 5 Gb/s data stream with the half rate clock, using both rising and falling clock edges. Since the 5:1 SR deals with the 10 bits input at low speed and the 2:1 MUX operates at half the speed of the data rate, the whole serializer could work at the high speed data rate with the lowest power consumption.

In order to implement a 2-tap pre-emphasis transmitter, delayed versions of the transmitter data must be created. This is accomplished with the PE shift register. The PE shift register consists of only two latches for the 2-tap pre-emphasis transmitter scheme. The latch clocked by CLK2 outputs the even and odd data for the main tap. The other one, clocked by CLK2b, generates the delayed and inverted even and odd data for the post cursor tap.

3.2 CM pre-emphasis output driver

Based on the comparison of Table 1, the CM output driver has good characteristics and is easy to implement with little overall power overhead. Hence, the CM pre-emphasis output driver is chosen in our design, as shown in Fig. 4. In order to save the power of the whole driver and maintain the driving capability, a reverse scaling technique is used. Moreover, we adopt the BCF technique to reduce the common mode noise. Two full rate data streams for the main stage and post cursor stage are first level-shifted from the 1.2 V power supply domain of the thin-oxide serializer to the 2.5 V domain of the thick-oxide output driver. Since the post cursor stage's current is much lower than the main stage, it is a scaled replica of the main stage.

3.2.1   Analysis of the output signal swing

Figure 5(a) shows a simplified schematic of the 2-tap CM pre-emphasis output driver, where the switches are implemented by the NMOS transistors. The signals A[0] and A[-1] denote the current and the previous bit and An[$\cdot$] appropriate bit inversions. When A[0]and An[-1] have the same data sign, the maximum output signal swing is produced. Assuming that the MOS transistors are ideal switches whose on resistances can be ignored, the $R_{\rm T}$ and $R_{\rm L}$ compose a current divider, as presented in Fig. 5(b). Then the maximum output signal swing is set to

$V_{\rm OD\_H} =I_{\rm Load} R_{\rm L} =\frac{R_{\rm T} (I_1 +I_2 )}{2R_{\rm T} +R_{\rm L}} R_{\rm L}.$

(1)

On the contrary, when A[0] and An[-1] are fed with the inversed data, a lower output signal swing is produced to implement the pre-emphasis. In this case, the equivalent circuit is shown in Fig. 5(c), and the output signal swing is defined by the equation

$V_{\rm OD\_L} =I_{\rm Load} R_{\rm L} =\frac{I_1 -I_2}{2+R_{\rm L}/R_{\rm T}} R_{\rm L}.$

(2)

In the fully matched case of $R_{\rm T}$ $=$ 50 $\Omega$, $R_{\rm L}$ $=$ 100 $\Omega$, Equations (1) and (2) become

$V_{\rm OD\_H} =\frac{1}{4}(I_1 +I_2) R_{\rm L},$

(3)

$V_{\rm OD\_L} =\frac{1}{4}(I_1 -I_2 ) R_{\rm L} .$

(4)

Therefore, by properly setting the value of the tail current $I_{1}$ and $I_{2}$, the CM output driver can achieve the desired pre-emphasis level ratio $V_{\rm OD\_H}$/$V_{\rm OD\_L}$ simply. The key feature is that the total current is a constant equal to $I_1$ $+$ $I_2$, in other words, when $V_{\rm OD\_H}$ and $V_{\rm OD\_L}$ is switching, no DDSC fluctuations occur, which relaxes the power supply regulator.

3.2.2   Reverse scaling

As mentioned in Section 2, the CM output driver should employ multiple pre-driver stages to guarantee the driving capability. However, the power and the bandwidth of the pre-driver could be the issues. If $n$ identical stages without pre-emphasis are cascaded, the current of the whole output stage is huge, i.e., 20$n$ mA for 1 V differential output swing. On the other hand, the level shifter will drive the large gate load of the pre-driver, which makes the level shifter design difficult.

Reverse scaling^{[11, 12]} provides bandwidth improvement in amplifiers and equalizers. In this paper, we introduce this concept for the output driver to save power and mitigate the load of the level shifter. As illustrated in Fig. 6, cascading of stages is scaled down in size by a factor of $\beta$ from the last stage such that the output swing of every stage is maintained to $I_{\rm T}$$R_{\rm T}$ while the load of the level shifter is reduced by $\beta^{n-1}$ times. The time constant of the $n$th stage is

$\tau _{k=n} =R_{\rm T} (C_{\rm L} +C_{\rm OUT} ),$

(5)

where $C_{\rm OUT}$ is the junction and overlap capacitance of the last stage, which is 50 fF, and $C_{\rm L}$ is parasitic capacitance of the ESD and pad, which is about 500 fF in our design. Thus, the bandwidth of the last stage is about 5.8 GHz, which is sufficient for our application. The corresponding time constant of the $k$th stage is given by

$\tau _{k<n}=\beta ^{n-k}R_{\rm T} \left(\frac{C_{\rm IN} }{\beta ^{n-k-1}}+\frac{C_{\rm OUT} }{\beta ^{n-k}}\right)\\\;\;\;\;\;\;\;=R_{\rm T} (\beta C_{\rm IN} +C_{\rm OUT}),$

(6)

where $C_{\rm IN}$ is the input capacitance of the last stage.

Obviously, the bandwidth of the pre-driver should be larger than the output stage, which means

$\tau _{k<n} <\tau _{k=n} .$

(7)

From Eq. (7), the relationship between $C_{\rm IN}$ and $C_{\rm L}$ can be expressed as

$C_{\rm L} \geqslant \beta C_{\rm IN} .$

(8)

In our design, $C_{\rm IN}$ $\approx$ 160 fF. Thus, $\beta$ $\leqslant$ 3.125. In order to save the power of the overall output driver, the value of $\beta$ should be as large as possible. Therefore, we design the $\beta$ $=$ 3, as shown in Fig. 4.

3.2.3   Bias current filtering (BCF)

As the high speed data sequence is pushed into the CM output driver, the noise will couple to the bias current with the same frequency and finally translates into a part of output common mode voltage noise. In PCIE 2.1, the variation of common mode voltage is specified to be less than 25 mV. The BCF technique, which is usually used in LC VCO design^[13], is adopted to the CM output driver in order to suppress the noise. As shown in Fig. 7, passive components $R_{\rm F}$ and $C_{\rm F}$ at the NMOS current mirror form a low-pass filter to suppress reference current noise and dynamic transient effects on the bias line. The whole CM output driver is simulated with the 5 Gb/s PRBS data input, and the results of output common mode voltage are shown in Fig. 8. The average common mode noise of the driver using BCF is about 31% less than the one without BCF (dashed).

4. Experimental results

The transmitter test chip is fabricated in 65 nm CMOS technology. For the ESD consideration, the output driver is fabricated in 280 nm thick-oxide technology. Figure 9 shows the die micrograph of the transmitter. The entire transmitter occupies an area of 240 $\times$ 140 $\mu$m$^{2}$, and operates at both 2.5 Gb/s and 5 Gb/s with the 1.2 V core and 2.5 V IO power supply.

A PRBS7 data stream produced by the on chip PRBS generator is sent to the transmitter. An Tektronix DSA 72004C digital analyzer is used to capture an eye diagram and measure jitter. Figures 10(a) and 10(b) show the differential eye diagram after passing though an 5 cm FR4 PCB trace, a connector, and a 1 m RG58 cable without pre-emphasis, at 2.5 Gb/s and 5 Gb/s, respectively. The total channel loss is 1.8 dB at 2.5 Gb/s and 4 dB at 5 Gb/s. The root mean square (RMS) jitter is 5.82 ps for 2.5 Gb/s and 9.94 ps for 5 Gb/s, the eye width can be achieved to 0.8 UIpp at both 2.5 Gb/s and 5 Gb/s; 60% thereof is deterministic jitter mainly due to period jitter which is caused by the spur of the clock and the intersymbol interference (ISI). The required eye height is greater than 800 mV at the transmitter output ports, and hence the measured far end eye height of 823 mV and 511 mV must be de-embedded at data rates of both 2.5 Gb/s and 5 Gb/s with a multiplication factor of 10$^{\rm 1.8\, dB/20}$ and 10$^{\rm 4\, dB/20}$, which results in an effective differential eye height of 1012 mV and 810 mV. Figure 11 presents the far end output eye diagram of the same channel at 5 Gb/s with 3.5 dB and 6 dB pre-emphasis. The RMS jitter is reduced to 7.49 ps and 7.07 ps respectively, which indicates that the pre-emphasis circuit has compensated the channel loss. The worst channel the transmitter could drive with 0 dB pre-emphasis is a 12 dB loss FR4 PCB differential snake wire, and a 16 dB loss wire with 6 dB pre-emphasis. The measured output common mode voltage is centered at 1.928 V and 1.920 V for 2.5 Gb/s and 5 Gb/s, respectively, and the variation is less than 10 mV.

The total power consumption of the transmitter with no pre-emphasis is 39.8 mA and 41.2 mA for 2.5 Gb/s and 5 Gb/s operation, respectively, which is much smaller than the identical stage pre-driver technique (60 mA only for output driver). The tiny difference between the two situations is mainly caused by the serializer (1.0 mA at 2.5 Gb/s and 2.2 mA at 5 Gb/s), while the output driver's power consumption is almost constant. This is because the power consumption of the serializer is proportional to the data rate, but the power dissipation of the output driver is defined by the output signal swing and the reverse scaling factor $\beta$, which are both constant. Based on the output signal swing analysis above, the relatively large current is caused by the large output swing specified in the standards. When pre-emphasis is adopted, the total power of the transmitter at 5 Gb/s is raised to 49.2 mA and 52.2 mA for 3.5 dB and 6 dB. The additional current, which is caused by the post cursor driver stages and the bias current, is obtained by Eqs. (3) and (4).

The performance of the overall transmitter is summarized in Table 2 and compared with prior works with similar architecture. Since the output driver, which dominates the bandwidth and the power consumption, is fabricated in 280 nm thick-oxide technology, the comparison with older technology work is meaningful. The reverse scaling output driver and the combined serializer largely reduce the power consumption. On the other hand, the widest eye width (EW) indicated a better SI performance of the overall transmitter.

5. Conclusion

In this paper, the comparison of two typical output driver architectures indicates that the CM output driver is suitable for high speed transmitter design due to its flexibility of controlling the output swing and the pre-emphasis level ratio. Also, based on the output signal swing analysis, the CM output driver has no DDSC fluctuations, which relaxes the power supply regulator. The large output swing specified in the standard dictates the use of a multiple stage pre-driver of the CM output driver, which will cause power and bandwidth issues. These issues can be mitigated by the reverse scaling technique. Additionally, bias current filtering (BCF) is adopted to suppress the output common mode noise. Furthermore, a high speed combined serializer architecture is implemented to relax the timing constraints with 10 bits input. The whole transmitter circuit is implemented in 65 nm CMOS technology. It provides an eye height greater than 800 mV for data rates of 2.5 Gb/s and 5 Gb/s, and the major parameters shown in Table 2 are fully compatible with the PCIE 2.0 and USB 3.0 standard specifications with significant margin. The experimental results show that the proposed techniques have good effects on the transmitter output signal and power efficiency.

Acknowledgement: The authors would like to thank the Tektronix Open Library for the test equipment.