1. Introduction

Organic field-effect transistors (OFETs) have attracted considerable attention because of their prominent features for realizing low-cost, large-area, mechanically flexible, and lightweight devices^[1-6]. The performance of OFETs has been improved rapidly in the last two decade. So far, much effort has focused on researching P-type OFETs, but only a few N-type OFETs have been reported^[7-9]. The most probable reason for this is that N-type material is relative unstable, and sensitive to oxygen and humidity^{[10, 11]}. In order to realize applications, such as in organic complementary logic circuits, both P-type and N-type transistors are needed and should have comparable performance^[12]. Therefore, further research is still needed to establish N-type OFETs in organic electronics.

Among N-type organic semiconductors, fullerenes hold great promise for high-mobility n-channel OFETs. Since the first report by Haddon et al.^[13] in 1995, improvements in the processing of C$_{60}$ have led to the demonstration of the highest electron mobility of 6 cm$^{2}$/(V$\cdot$s) by Anthopoulos et al.^[14] in C$_{60}$ films deposited by hot wall epitaxy at an elevated temperature of 250 ℃. By modifying the properties of the C$_{60}$/SiO$_{2}$ interface using pentacene, Itaka et al.^[15] obtained an electron mobility of 4.9 cm$^{2}$/(V$\cdot$s) in devices processed at 50 ℃ and tested in high vacuum, and the devices exhibited an ambipolar property due to the presence of the pentacene wetting layer. Though their devices possess high mobilities, the fabrication needs special conditions. Thus common experience methods, such as thermal evaporation, are required to achieve N-type OFETs.

In general, the performance of OFETs is not governed solely by the materials or structural options, whereas it is largely influenced by the interface modified layers. It is well known that OFETs work in the accumulation region, and that most of the modulated charge lies in the semiconductor near the semiconductor/dielectric interface. The interaction between the gate dielectric and the semiconductor layer plays an important role in the formation of carrier transport. So far, many groups have reported different methods to modify semiconductor/dielectric interfaces, including introducing an ultrathin polymer passivation^[16] and inserting a small molecule material thin film^[17], and so on. However, further research is still of great significance because it is difficult to provide a simple and effective way to improve the morphology of the semiconductor and to fill the traps of the gate dielectric to make the devices available for real applications.

In this paper, we demonstrate top-contact C$_{60}$-based OFETs by inserting a pentacene passivation layer between C$_{60}$ and the gate dielectric. After the modification of the 2 nm pentacene passivation layer, the enhanced performance is observed. The peak field-effect mobility is up to 1.01 cm$^{2}$/(V$\cdot$s) and the on/off ratio shifts to 10$^{4}$.

2. Experiment

Figure 1(a) shows a schematic diagram of C$_{60}$-based OFETs. Figures 1(b) and 1(c) show the molecular structures of pentacene and C$_{60}$, respectively. The devices were prepared on indium-tin-oxide (ITO)-coated glass as the gate electrode and substrate. The substrate was cleaned with deionized water, acetone, and isopropanol in turn, and then a spin-coating 390 nm polymethyl methacrylate (PMMA) was used as the gate dielectric. The substrates with PMMA were transferred to a glove box and annealed on a hot plate at 120 ℃ for 2 h. An ultrathin pentacene passivation layer was thermally deposited first with a deposition rate of approximately 0.3 Å/s. In succession, a 40 nm C$_{60}$ thin film was thermally evaporated at a deposition rate of 0.6 Å/s. Finally, the 150 nm Al source and drain electrodes were thermally evaporated through a shadow mask. The channel length ($L)$ and width ($W)$ were 80 $\mu$m and 4 mm, respectively, and all of the organic layers and source-drain electrodes were grown at a base pressure of 10$^{-4}$ Pa. The electrical characteristics were measured using two Keithley 2400 source meters and a Keithley 485 picoammeter at room temperature under ambient atmosphere conditions.

3. Results and discussion

Figures 2(a) and 2(b) show the output and transfer characteristics, respectively, of C$_{60}$ OFETs without the pentacene passivation layer. Though the linear and saturation regions are observed with the increase in drain voltage ($V_{\rm ds})$, the output current is only is 1.18 $\times$ 10$^{-5}$ A at a 60 V gate voltage ($V_{\rm g})$. Figures 3(a) and 3(b) show the electrical characteristics of the devices with a 2 nm thick pentacene passivation layer. The device exhibits typical n-channel operational characteristics, and the smooth $I_{\rm ds}$-$V_{\rm ds}$ curves are observed. When the gate voltage ($V_{\rm g})$ is kept at 60 V, the output current ($I_{\rm ds})$ reaches 4.13 $\times$ 10$^{-4}$ A. Compared with the bare interlayer, the output current ($I_{\rm ds})$ values are higher by more than one order of magnitude.

The field-effect mobility ($\mu$) of the device may be estimated from the relation between the saturated source-drain current $I_{\rm ds}$ and $V_{\rm g}$,

$\begin{equation} \label{eq1} I_{\rm ds} =\frac{W}{2L}\mu C_{\rm i} (V_{\rm g}-V_{\rm th})^2. \end{equation}$

(1)

Here, $W$ represents the channel width, $L$ the channel length, $\mu$ the field-effect mobility, and $C_{\rm i}$ the gate capacitance per unit area of the PMMA dielectric. The capacitance value of the PMMA insulator is 6.81 nF/cm$^{2}$. $V_{\rm g}$ is the gate voltage, $V_{\rm th}$ is the threshold voltage, and $I_{\rm ds}$ is the saturated drain current. Using Eq. (1), the saturated field-effect mobility of the device with the PMMA-only dielectric can be calculated to be 2.13 $\times$ 10$^{-1}$ cm$^{2}$/(V$\cdot$s). After incorporating with 2 nm pentacene passivation, the peak field-effect mobility reached 1.01 cm$^{2}$/(V$\cdot$s). But when the thickness of the pentacene passivation layer was more than 2 nm, the saturated field-effect mobility of the device began to decline. The results indicate that the field-effect mobility of the device increases as the thickness of the pentacene passivation layer increases from 0 to 2 nm, and then decreases as the pentacene passivation layer thickness increases to 4 nm, as shown in Fig. 4. This variety in the field-effect mobility reveals that N-type transport is enhanced with the optimized thickness of the pentacene passivation layer. Table 1 shows a summary of the performance parameters for the devices with and without the pentacene passivation layer. This means that the pentacene passivation layer plays a key role in the performance of the device.

In order to understand the enhancement of the device mobility, the surface morphologies of the C$_{60}$ films with and without a pentacene passivation layer were examined by an atomic force microscope (AFM). Figures 5(a) and 5(b) show AFM images of C$_{60}$ (40 nm)/PMMA and C$_{60}$ (40 nm)/pentacene (2 nm)/PMMA films, respectively. As shown in Fig. 5(b), the larger C$_{60}$ grain size is observed. The grains grow to an average size of about 106 nm in the 1 $\mu$m square area, which indicates that the grain boundary is seriously decreased. Usually, many traps are concentrated on the grain boundary, which can capture the charge carriers. At this point, the larger grain size of the C$_{60}$ film on the pentacene passivation layer should have less of a grain boundary, leading to fewer traps. Thus, a lower grain boundary can transport carrier charges more easily and the field-effect mobility of the devices is improved.

Based on the above results, after inserting the pentacene passivation layer, we consider that two reasons can influence the performance of the devices. One may be that the pentacene passivation layer can reduce charge trapping to make the charge carriers easier to transport. The other is that the morphology and crystallinity of the C$_{60}$ film can be changed, and then charge carrier transport can be improved.

4. Conclusion

In summary, we demonstrated the effect of a pentacene passivation layer between the C$_{60}$ active layer and the gate dielectric in N-type OFETs. The device performance can be enhanced by modifying the pentacene passivation layer. A high electron mobility of up to 1.01 cm$^{2}$/(V$\cdot$s) and on-off ratio of 10$^{4}$ were obtained. The increase in the C$_{60}$ film grain size with the insertion of a pentacene passivation layer is believed to be the reason for the improved performance. Therefore, using a pentacene passivation layer is an effective and simple method to prepare high-performance n-channel transistors for practical application.