1. Introduction

With the rapid development of wireless network technology, computer technology and high-speed data acquisition technology, the speed of digital signal processing has greatly improved over time, which has led to a large increase in the requirements for data conversion rates. Therefore, high-speed analog-to-digital converters (ADCs) have received significant attention, and the demand for high-speed/wideband ADCs is rapidly increasing. Among all the ADC blocks, the track-and-hold amplifier (THA), located at the front end of the ADC, is a critical component because it will affect the overall performance of the ADC. The THA can overcome the limitation on the analog signal bandwidth of ADCs and account for the linearity degradation from the long settling time and nonlinear parasitic to reduce timing jitter. Therefore, the design of a high-speed THA is very important in the realization of high-speed digital equalizers.

Several high-speed SiGe THAs with different operational ranges and linearity performance have been reported recently^[1-7]. For instance, a 40 GS/s SiGe THA with a switched-emitter-follower (SEF) configuration and a low-noise input preamplifier was presented in Ref.[1]. A SiGe THA with an improved version of the pseudo-differential structure was reported in Ref.[2], and achieves a total harmonic distortion (THD) of -52.4 dBc at a sampling rate of 12.1 GS/s, and is the fastest 8-bit Si-based THA achieved to date. Reference[3] employed three-stage SEF architecture to realize a distributed SiGe THA that achieves the fastest sampling rate demonstrated to date, 50 GS/s. From this reference, a popular high-speed SiGe THA architecture employs a (bipolar-based) SEF structure. The SEF can operate at very high speeds, while maintaining good linearity, due to the high linearity, high $f_{\rm T}$, low leakage, and good matching properties of bipolar transistors compared with their CMOS counterparts, although it requires a larger supply voltage than is necessary or desirable for integrated digital logic.

To achieve high-speed operation, open-loop architecture is preferred over closed-loop architecture because the latter has a global feedback that will inevitably decrease the speed in order to meet the stability and settling requirements. In this paper, an open-loop ultra-high-speed THA operating at a sampling rate of up to 20 GSps is presented. Realized with CMOS and dummy switch structure and a fully differential configuration, this THA employs cross-coupled pairs in a common-source amplifier to suppress the charge injection and clock feedthrough in the tracking mode^[8]. The active inductor is used as the load to improve the signal bandwidth. The THA was fabricated in 0.18 $\mu$m SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply to decrease the power dissipation, and the power consumption is 77.9 mW.

2. Track-and-hold amplifier design

Figure 1 shows a block diagram of the proposed track-and-hold amplifier in this paper. It is composed of three cascaded stages. The input stage is realized by a differential common-source amplifier with the cross-coupled pairs matched to 50 $\Omega$. A CMOS switch and double dummy switch provide the track-and-hold block. The output stage is a large bandwidth linear driver, which is designed to drive the off-chip 50 $\Omega$ load. The proposed THA has open-loop architecture to improve its operational speed, and a fully differential configuration is employed to mitigate the common-mode noise and suppress the even-order harmonics.

In a THA, the input buffer is an important block because a high speed and linearity input buffer can improve the performance of the whole THA. A differential common source amplifier is used in this work, and is shown in Fig. 2. This structure is chosen because it results in a large bandwidth and it is easy to achieve a gain close to 1 with the open-loop stage. The differential pair M1, M2, form the input buffer and are minimal length NMOS pairs. The widths were designed to obtain high-frequency operation, satisfying the THA demand and keeping low power consumption.

In order to achieve high linearity in the input buffer, a cross-coupled pair consisting of M3 and M4 is used to decrease the charge injection and clock feedthrough in the tracking mode, shown in Fig. 2 by the dotted line^[9]. As shown in Fig. 2, an error voltage $\Delta V$ is added on the input signal. Then, the output voltage $V_{\rm on}$ with and without cross-couple can be calculated, and is shown in Eqs. (1) and (2), respectively.

$\begin{array}{l} {V_{{\rm{on}}, {\rm{withcrosscouple}}}} = - {g_{{\rm{m1}}, {\rm{2}}}}({V_{{\rm{inn}}}} + \Delta V)Z\\ \;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\; + [-{g_{{\rm{m1}}, {\rm{2}}}}({V_{{\rm{inp}}}} + \Delta V)Z(-{g_{{\rm{m3}}, {\rm{4}}}}Z)]\\ = - {g_{{\rm{m1}}, {\rm{2}}}}[(1 + {g_{{\rm{m3}}, {\rm{4}}}}Z){V_{{\rm{inn}}}} + (1-{g_{{\rm{m3}}, {\rm{4}}}}Z)\Delta V)]Z, \end{array}$

(1)

$V_{\rm on, without cross couple} = -g_{\rm m1, 2} (V_{\rm inn} +\Delta V) Z,$

(2)

where $g_{\rm m1, 2}$ is the transconductance of the differential NMOS pair, M1 and M2, $g_{\rm m3, 4}$ is the transconductance of the differential NMOS pair, M3 and M4, $V_{\rm inn}$ and $V_{\rm inp}$ are the differential input voltages, $\Delta V$ is the error voltage caused by clock feedthrough and charge injection, and $Z$ is the output impedance. Comparing Eq. (1) with Eq. (2), a factor of (1 -$g_{\rm m3, 4}$ $Z)$ is multiplied to the error voltage $\Delta V$ in Eq. (1). Therefore, we can design the output impedance and transconductance of M3 and M4 to make the absolute value of (1 -$g_{\rm m3, 4}$ $Z)$ less than 1. Thus, the error voltage is reduced with the cross-coupled pair. The DC response simulation result is shown in Fig. 2. The input amplifier has good linearity when the input amplitude is up to 600 mV.

Because the passive inductor is always very large and the inductance of the passive inductor is hard to change, an active inductor is realized by M5 and $R_{\rm g}$ (M6 and $R_{\rm g})$ as the load that can extend the signal bandwidth. The simplified equivalent circuit of the active inductor is shown in Fig. 2. From the equivalent circuit of the active inductor, the equivalent impedance can be denoted as

$Z=\frac{1+RsC_{\rm gs} }{g_{\rm m} +sC_{\rm gs} },$

(3)

and we can calculate the expressions of $L$, $R_{1}$ and $R_{2}$, which are denoted as^[10]

$L\approx C_{\rm gs} (G_{\rm g} -1/g_{\rm m})/g_{\rm m},$

(4)

$R_1 \approx R_{\rm g} -1/g_{\rm m},$

(5)

$R_2 \approx 1/g_{\rm m},$

(6)

where $C_{\rm gs}$ and $g_{\rm m}$ are the gate-to-source parasitic capacitance and the transconductance of the nMOS transistor, respectively. The value of $R_{1}$ approximately equivalent to $R_{\rm g}$ due to 1/$g_{\rm m}$ is usually very small. Therefore, we can choose the resistor $R_{\rm g}$ and transconductance $g_{\rm m}$ of the nMOS transistor to extend the bandwidth based on Eqs. (4)-(6).

In order to cancel the clock feedthrough, there are various circuit topologies^{[11, 12]}, such as the CMOS switch, dummy switch, bootstrap switch, and so on. However, some of the methods are not suitable for high-speed application. In this paper, transistors M1 to M6 constitute a CMOS switch and a dummy switch that carries out the actual sampling function and decreases the clock feedthrough. The circuit is shown in Fig. 3. The transmission gate with M1 and M2 is the main switch that worked with complementary clock signals. The other transmission gates consisting of M3, M4, M5 and M6 are the dummy switches for input and output error cancelling. The sizes of the dummy devices are about half of M1 and M2, respectively, and will provide opposite charge in the input and output paths to decease the injection charge and contribute to the error elimination. When the clock is high, the CMOS switch is on and the switch on-resistance $R_{\rm on, CMOS}$ is a constant and small, which is good for high speed and noise suppression.

A pseudo-differential common source structure, presented in Fig. 4, is chosen to design the output buffer. The transistors are biased at a peak $f_{\rm T}$ current density for maximum speed, and the high current density allows improved linearity with a sufficient bandwidth. Similar to the input stage, the output stage using the active inductor is designed to extend the bandwidth. The simulation result is shown in Fig. 4, and the $\omega_{\rm -3dB}$ of the output buffer reaches 37 GHz, which is good for improving THA performance. The differential pair also allows the elimination of the parasitic common mode created in the sampling mode between the two differential signals.

3. Measurement results

The proposed THA circuit was designed and fabricated in a HHNEC 0.18 $\mu$m SiGe BiCMOS process and only MOSFETs were used. Figure 5(a) shows the chip microphotograph of this THA. The total chip size is 710 $\times$ 410 $\mu$m$^{2}$, including the testing bondpads, and the core area only 200 $\times$ 120 $\mu$m$^{2}$. In the test, an Agilent 81250 signal generator was used to generate the differential clock frequency. A 0.5-12 GHz balun was used in the input port to connect the 0.01 to 40 GHz Rohde-Schwarz SMP04 signal generator as differential input sinusoidal signals. A BiasT was also used to provide the input bias voltage. The measurement setup is shown in Fig. 5(b). The total power consumption is about 77.9 mW, with the output buffer at a 1.8 V supply.

Time domain measurements were conducted using a Tektronix DPO 72004C oscilloscope. The two outputs of the THA were displayed on channels 1 and 2, respectively, and the differential output was calculated using the scope's built-in functions. Figure 6(a) shows the differential output of the 2 GHz signal sampled at 20 GHz, while Figure 6(b) shows both the single ended and differential outputs of the 4 GHz signal sampled at 20 GHz. The input power is 0 dBm. As shown in Fig. 6(b), the clock feedthrough is obvious and the maximum single-ended clock feedthrough is 48 mV, which is significantly reduced in the differential measurements.

The spectral content of the output signal was captured using an Agilent E4448A PSA spectrum analyzer. Figure 7 shows the measured differential output spectrum of the THA operating at a sampling rate of 20 GSps, with a 4 GHz input frequency. It can be seen from this figure that the second-order harmonic distortion is suppressed, which is a direct consequence of the fully differential design and the symmetrical layout employed in the design. The measured SFDR is 32.4 dB under these measurement conditions and the third harmonic distortion is -48 dBc. Figure 8 plots the SFDR and THD of the differential output with input frequency $f_{\rm in}$ versus the sampling frequency $f_{\rm s}$, where the SFDR is larger than 24 dB at Nyquist sampling, which means that the THA's effective number of bits (ENOB) exceeds 4 bits.

The spectral characteristics of the beat frequency test are also implemented with distributed topologies to $f_{\rm in}= f_{\rm s}+\Delta f$, where $f_{\rm s}$ $=$ 12 GHz and $\Delta f$ $=$ 2 MHz at an input power of -3 dBm. This is shown in Fig. 9 with the third-order harmonic distortion better than -70 dBc, the SFDR better than 20 dB, and the THD is -24 dBc.

A widely used performance measure for THA is the following figure of merit (FOM), including the power dissipation, effective resolution and sampling speed, which can be expressed as FOM $=$ $P_{\rm diss}$/(2$^{\rm ENOB}f_{\rm s})$, where ENOB is the effective number of bits, $f_{\rm s}$ is the sampling rate, and $P_{\rm diss}$ the power consumption of the THA. The measured results of this SiGe THA are summarized in Table 1. A comparison was also made between this SiGe THA and some of the THAs found in the literature. It can be seen that the present SiGe THA has a wide operational range, with comparable characteristics to other THAs operating under different conditions. Compared to the THAs published in the literature with operational frequencies of up to 20 GSps, the present THA demonstrates a FOM and power consumption that is comparable to the best achieved.

4. Conclusion

A low-power 20 GSps THA circuit was verified in a 0.18 $\mu$m SiGe BiCMOS process. The circuit used only CMOS transistors at a 1.8 V voltage supply to decrease the power dissipation, and the power consumption was only 77.9 mW. An open-loop fully differential structure was adopted to mitigate common-mode noise and suppress even-order harmonics. A CMOS switch and dummy switch was used to achieve high speed and decrease clock feedthrough. The experimental results showed that the sampling speed can reach up to 20 GSps, and that the SFDR exceeds 30 dB when the input frequency is 4 GHz at 20 GSps. The measurement results indicate that the presented THA is suitable for use in ultra-high-speed analog-to-digital converters and low-power applications.

Acknowledgments: The authors would like to thank Zhang Li for help in checking the layout and design analysis tutoring, and Li Wei for assistance with the chip testing.