1. Introduction

Frequency multiplier, and in particular frequency doubler, is widely used in millimeter-wave signal sources and transceivers. It can be used to extend the frequency range of microwave signal sources up to millimeter-wave band while maintaining the performances of the microwave signal sources, such as high stability and low phase noise^[1]. As frequency increases from microwave to millimeter-wave, the influence of the parasites in devices and passive structures become dramatically stronger. Therefore, the design of a W-band doubler presents remarkable challenges and specific methodology should be applied.

A traditional distributed diode multiplier often occupies large areas and requires high driving power^{[2, 3]}. Nowadays, the progress of semiconductor technologies based on both specific materials and proper scaling of devices enables us to concentrate on the design using the current-source biased differential pairs in MMIC.

In this paper, the authors present the design, fabrication, and characterization of a MMIC frequency doubler which theoretically operates from 75 to 110 GHz (due to the upper-frequency limit of the signal source, the doubler was characterized with the frequency only to 80 GHz). To implement the frequency doubler, an active differential balun is chosen to convert the single-ended input to differential output. The final push-push stage performs frequency doubling and suppresses the fundamental frequency. This differential-pair architecture allows us to achieve good fundamental signal rejection and fairly high output power. Multi-stage differential structure improves the conversion gain and diminishes the impact of the active balun's unbalance on the circuit performances.

The InP double heterojunction bipolar transistor (DHBT) technology, used for doubler fabrication, is presented, and the doubler design is given.

2. Technology

The transistor is grown on 3-inch InP wafer with an epitaxial profile designed for high frequency application. $S$-parameter measurements of the 1 $\times$ 15 $\mu$m$^{2}$ HBT demonstrates an extrapolated $f_{\rm T}$ (current gain cutoff frequency) of 170 GHz and an extrapolated maximum oscillation frequency $f_{\rm max}$ of 253 GHz at the bias of $I_{\rm C}$ $=$ 15.4 mA and $V_{\rm CE}$ $=$ 1.5 V^{[4, 5]}. The large-signal model for InP/InGaAs DHBTs has been implemented as a symbolically defined device (SDD)^[6] in the Agilent ADS simulator.

The InP DHBT IC process includes MIM capacitor, thin-film resistors (50 $\Omega$/$\square$), 2-levels of interconnect (M1, M2), benzocyclobutene (BCB) passivating devices, and the wafer planarization after device formation, as shown in Fig. 1. A coplanar waveguide (CPW) is employed for its widely controllable impedance, ease of fabrication, and ability to maintain signal integrity at very high frequencies within dense mixed-signal ICs.

3. Circuit design

The frequency doubler is based on a push-push cell which outputs the second harmonic wave and suppresses the fundamental power. Frequency doubling results in generating harmonics due to nonlinear characteristics of the transistors in the push-push structure^[7] and the former common-emitter stage working under large-signal condition.

3.1 Circuit architecture

A detailed electrical scheme of the proposed doubler IC is illustrated in Fig. 2.

The chip consists of five building blocks such as current mirror, active balun, differential amplifier, emitter follower and push-push core. The current sources are used to bias the emitter followers and differential pairs. For differential structure, this presents high common-mode impedance and improves the common-mode rejection ratio. The single-ended input is first transformed into differential output by the active balun and amplified by the following common-emitter stage. Then, the amplified signals are buffered by the emitter follower and used to drive the push-push frequency doubling core.

3.2 Electrical design

Negative bias $V_{\rm EE}$ is employed so that the collectors of Q3-Q10 can connect to ground instead of DC bias lines. In this way the influence of the bias network on the RF path is minimized. Active differential balun instead of passive balun is used by virtue of its compact size. The balun loses its amplitude and phase balance as frequency increases since the bases of Q3, Q4 see different impedances when the signal source is connected^[8]. Following the differential balun, the common-emitter differential amplifier and the emitter follower help to diminish this mismatch. Also the emitter follower stages realize a level shifting and impedance matching to the next stage. Transmission lines T1, T2 provide an impedance match for fundamental frequency and can also reflect back the harmonic frequencies coming from the doubling stages.

Frequency multiplication occurs in the push-push core, as shown in Fig. 3. Q9 and Q10 are biased close to class-B ($V_{\rm BE}$ $=$ 0.82 V), serving as the doubling core. The harmonic component of collector current is a function of conduction angle, which can be controlled by the input driving power and the base bias point^[9]. The collector current can be modeled as a train of rectified cosine pulses as shown in Fig. 4and using the Fourier series expansion, it can be represented as^[10]

$\begin{array}{l} {I_{\rm{c}}}(t) = {I_0} + {I_1}\cos \left( {{\omega _1}t} \right) + {I_2}\cos \left( {2\omega t} \right) + \cdots \\ \;\;\;\;\;\;\;\;\;\;\;\;\; + {I_n}\cos \left( {n\omega t} \right) + \cdots, \end{array}$

(1)

$I_0 =I_{\rm max} \frac{4t_0 }{\pi T},$

(2)

$I_{\rm n} =0, \;{\rm for\; odd}\; n,$

(3)

$I_{\rm n} =I_{\rm max} \frac{8t_0 }{\pi T} \left( \cos \frac{n\pi t_0 }{T} \right) \left[ 1-\left( {\frac{2nt_0}{T}}\right)^2 \right]^{-1}, \, {\rm for}\; {\rm even}\; n.$

(4)

$I_{\rm max}$ is the maximum current, $t_{0}$ is the length of the pulse, and $T$ is the period corresponding to the fundamental frequency. To maximize the amplitude of the second harmonic, the conduction duty cycle for each transistor should be chosen such as $t_{0}$/$T$ $=$ 32%^[9]. However, this would sacrifice the valuable gain at W-band. As a compromise, Q9, Q10 were each biased with $t_{0}$/$T$ about 50%. Simulation of the push-push core is shown in Fig. 2and we show the collector currents $I_{\rm C1}$, $I_{\rm C2}$ in Fig. 5. Q9 and Q10 turn on alternately and at the output node the circuit delivers the even-order harmonic current or voltage, as shown in Fig. 6. The fundamental leakage is due to the non-ideal differential characteristics of the signals at the two bases of Q9 Q10. This comes from the imbalance of the active balun.

Current mirrors act as stable current sources. The parallel short-ended stub T3 with electrical length of 24$^\circ$ @ 2$f_0$ ($f_0$ $=$ 90 GHz) at the common collector node implement the simple impedance match for the doubling frequency. T3 can also ground the fundamental frequency $f_0$ thus improving the fundamental suppression.

All transistors have a size of 1 $\times$ 15 $\mu$m$^{2}$, which is a good compromise between $f_{\rm T}$ and RF power. Q1, Q2 are biased at 5 mA and 7 mA respectively with $R_{1}$ $=$ 300 $\Omega$, $R_{2}$ $=$ 120 $\Omega$, $R_{3}$ $=$ 500 $\Omega$ which stabilize the current source in case of environment variation. Q2 helps to reduce the base current influence and improve the output current precision. The individual source for the differential structure is biased at about 14 mA to make full use of the DHBT's gain and power ability.

Due to circuit complexity and wide frequency band of DHBT, circuit stability is an important design issue. When frequency increases toward W-band, the current source loses its high-impedance characteristics and even presents some immittance. Also the parasitic inductances or capacitances of the devices and the interconnecting lines have an even greater impact on the RF performance. Hence, wires connecting the current sources to the differential pairs are modeled as transmission lines in the schematic diagram. Also the stabilizing resistors $R_{\rm c1}$, $R_{\rm c2}$ are included to eliminate the oscillations. These are shown in Fig. 7.

All the passive components, including capacitances, resistors and transmission lines, are simulated by momentum electro-magnetic (EM) simulator, and then co-simulated with the nonlinear HBT models in Agilent's advanced design system (ADS) EDA environment to predict the time-domain and frequency-domain output. Figure 8 shows the simulated frequency spectrum and wave form of the output signal when the driving signal is of 40 GHz and 0 dBm.

3.3 Layout design

The whole circuit is divided into two parts: RF core and DC bias. The RF core contains four pairs of HBTs Q3-Q10, matching transmission lines T1-T3, and RF input and output ports. The DC part is composed of current mirrors which are used to bias the RF differential pairs.

The signal line is fed via the matched 50 $\Omega$ CPW line. Similarly, the output signal is connected to the output pad with a 50 $\Omega$ CPW line. The layout is compacted to shorten high-frequency signal paths. The RF core is optimized for minimum wire length and maximum symmetry. $V_{\rm EE}$ feeds the RF transistors through the current mirror sources which isolates the RF core from DC bias lines. The microphotograph is presented in Fig. 9 with a size of 0.55 $\times$ 0.5 mm$^{2}$.

4. Test and measurements

The doubler was measured using on-wafer probing and biasing at room temperature, as shown in Fig. 10. The input signal was generated by a signal generator (E8257D) and delivered to the MMIC through coaxial cables. The output signal was delivered to the 18th harmonic mixer through a GGB WR-10 waveguide and down-converted to Ka-band. The output signal was monitored by spectrum analyzer (E4447A) with the frequency value displayed at W-band. The bias voltage $V_{\rm EE}$ for all stages is -3.6 V and the total current $I_{\rm EE}$ is 113 mA. So the power consumption is 407 mW.

Figure 11 gives the output spectrum when the input frequency is 80 GHz. From the displayed noise level and the resolution bandwidth (BW), it can be estimated that the phase noise is about

$\begin{array}{l} {\rm{Noise}}{\mkern 1mu} ({\rm{dBm}}) - {P_{{\rm{out}}}}{\mkern 1mu} ({\rm{dBm}}) - 10\lg ({\rm{BW}}({\rm{Hz}}))\\ \;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\; \approx {\rm{ - 120}}{\mkern 1mu} {\rm{dBc/Hz}}{\mkern 1mu} @\;{\mkern 1mu} {\rm{1}}\;{\mkern 1mu} {\rm{MHz}}, \end{array}$

(5)

which is very close to the theoretical value of the 18th multiplied E8257D signal:

$-146\, (\rm dBc/Hz)+20\lg 18=-121\, ({\rm dBc/Hz).}$

(6)

From Eqs. (5) and (6), it is certain that the additive phase noise of the frequency doubler is trivial and will not aggravate the quality of the input signal.

The output spectrum was also inspected from 10 MHz to 42 GHz to determine the fundamental frequency suppression. When the input power is 0 dBm @ 40 GHz, form Fig. 12, it can be seen that the displayed power of the fundamental frequency is $-21.4$ dBm. With the 9.5 dB coaxial cable loss taken into account, the actual power of the fundamental frequency is $-10.9$ dBm.

Figure 13 shows the measured output power and conversion gain for various input power at 80 GHz. It can be seen that at the vicinity of $-7$ dBm for input power, the output power began increasing rapidly and the fundamental wave came into compression. This indicates that the doubler was driven effectively and nonlinearity was strengthened. Hence the second harmonic frequency was triggered out. When the input signal reached $-2$ dBm, conversion gain exceeded 0 dB. With the input power increased further, the output power saturated at about 6 dBm, with the corresponding gain of 5 dB.

The output power and conversion gain are also measured as a function of the input frequency, as shown in Fig. 14. As can be seen, from 75 to 80 GHz, the conversion gain is more than 4.7 dB and output power is higher than 5.8 dBm with gain-ripple less than 0.6 dBpp. The output spectrum with the input frequency swept from 37.5 to 40 GHz was also inspected. The final results are also shown in Fig. 14. As can be seen, suppression of the fundamental frequency is below -16 dBc, which is close to the predicted -19 dBc in Fig. 8. The small-signal $S_{22}$ is below -6 dB over the whole W band.

A comparison of several representative reported W-band frequency doublers is presented in Table 1. Contributing to the low-parasite design of the multi-stage differential structure and high frequency performance of the InP DHBT, the proposed doubler demonstrates the highest conversion gain.

5. Conclusion

A compact W-band frequency doubler using push-push shaping circuit is proposed. Differential structure improves the common-mode rejection ratio and suppresses fundamental frequency. The multi-stage driving circuit increases the conversion gain and delivers enough power to the push-push core. Low-parasite layouts ensure the desirable RF performance. Due to the frequency limit of the test system, measurements were performed from 75 to 80 GHz and show the output power is higher than 5.8 dBm with conversion gain above 4.7 dB.