1. Introduction

Wireless communication systems including wireless sensor networks lead to a huge market of RF CMOS circuits, and the circuits with less power consumption are more competitive. The Zigbee transceiver aims at low power applications, whose operation frequency range is 2.4-2.485 GHz. The voltage controlled oscillator (VCO) performs frequency modulation in the transmitter and the local oscillator (LO) in the receiver, whose power dissipation is limited by 3.6 mW in our Zigbee project, and the phase noise at 10 kHz and 1 MHz could not be larger than -70 dBc/Hz and -120 dBc/Hz, respectively. When VCO is used in the frequency synthesizer for the receiver, the frequency tuning is expected to be linear. It is challenging to design such low phase noise VCO with low power, while the area could not be too large for cost consideration.

Among various studies of VCO in the last ten years, LC VCO has been widely adopted in Giga Hz frequency and beyond for its better noise performance than ring oscillator and others. Figure 1(a) shows the conventional LC VCO with tail current source. The current source NM0 is biased by fixed voltage and operates in the saturation region. The current is well controlled, but noise coupled in through the gate of NM0 and the current source becomes a main contributor of phase noise. Obviously it also reduces voltage headroom, which is not good for low voltage supply application. To reduce phase noise, current source is removed, as shown in Fig. 1(b), and the voltage headroom is maximized. However, the power consumption increases, and the absence of high impedance in the tail leads transistors in the triode region to load the resonator. Reference [1] proposed a filtering technique to lower phase noise effectively by adding an LC tank oscillating in second harmonic at the tail node, but the additional inductor and capacitor consume a large area.

The main sources of phase noise in VCO are thermal noise and flicker noise of MOSFETs. To reduce close-in phase noise, people pay more attention to flicker noise^[2-5]. Especially in deep submicron or nano-scale CMOS process, flicker noise plays a significant role in phase noise as device size reduces significantly^[6]. It is straightforward to reduce flicker noise by large transistor size and small transconductance^[7]. However, large size transistors limit the frequency tuning range, and the start-up condition is difficult to meet for small transconductance. So, further study for flicker noise reduction is needed.

Flicker noise of the transistor can be reduced by switching on and off periodically, as shown in Fig. 2, which will lessen "long-term memory" physically^{[2, 3]}. This switched biasing technology is applied to differential VCO^[4] and quadrature VCO^[5], which reduces phase noise effectively at the cost of more than two times power consumption.

The varactors in VCOs shown in Fig. 1 usually leads to non-linear frequency tuning characteristics and variation of gain, which could not fit our design requirement, thus additional technology should be used.

In this paper, self-switched biasing technology and a decoupling capacitor are used to reduce flicker noise from tail bias transistors and suppress noise up-conversion from the cross-coupled pair, which also helps to produce a low power design by exploiting its operation feature. Linearized tuning characteristics are achieved by distributed biasing varactors.

2. Circuits design and optimizations

2.1 Phase noise reduction

Based on previous discussions, a differential LC VCO with low phase noise is proposed as shown in Fig. 3. Complementary differential typology is adopted, where cross-coupled pairs NM1, NM2 and PM1, PM2 supply negative resistance; NM3, NM4 work as tail bias transistors.

Coupling capacitors $C_{1}$, $C_{2}$ provide AC path for switched biasing, by which the oscillation output voltage VO$+$, VO$-$ inject into the gate of tail current transistors NM3, NM4, thus the gate voltage of NM3, NM4 varies according to oscillation voltage, and they are switched on and off periodically. DC bias of the gate voltage is given by $V_{\rm B}$, which is used to set the operation state of tail bias transistors. From noise contributions of Cadence Spectre simulation, intrinsic flicker noise in tail bias transistors is reduced significantly.

Up-conversion of flicker noise from the cross-coupled pair also impacts phase noise, including indirect FM by nonlinearity of the transistor^[7], AM-PM conversion by nonlinearity of the varactors^[8], and second harmonic modulation at the tail capacitor^[9]. To suppress flicker noise up-conversion, decoupling capacitor $C_{0}$ is inserted between source nodes of NM1, NM2. According to Ref. [9], $C_{0}$ will create a fundamental frequency component, whose amplitude would be comparable with the second harmonic component at the source if it is with proper capacitance. This can decouple the fluctuating offset voltage across the source of the cross-coupled pair, thus flicker noise no longer modulates the second harmonic at source node, and the up-conversion of flicker noise from the cross-coupled pair will be suppressed.

$C_{3}$, $C_{4}$ are parallel with $C_{\rm gs}$ of NM3, NM4, which perform low pass filtering with $R_{1}$, $R_{2}$, and the noise from the bias path is filtered out, leading to better phase noise at 1 MHz offset. The capacitance should not be too large, otherwise the impedance of the tail bias transistor would decrease, and the quality factor Q of the resonator would be degraded as cross-couple transistors in triode region^[1].

Simulated phase noise of conventional VCO (Fig. 1(a)) and proposed (Fig. 3) are shown in Fig. 4. For fair comparison, they work at the same oscillation frequency and dissipate the same power. There is about 11 dB improvement of phase noise at 10 kHz offset by the proposed, and 4 dB improvement at 1 MHz offset. The significant improvement of close-in phase noise, which is dominated by flicker noise, confirms the positive effect of proposed VCO for flicker noise reduction.

2.2 Power consumption optimization

For self-switched biasing oscillator (shown in Fig. 3), the gate-source voltage of the tail current transistor is a summation of DC bias $V_{\rm B}$ and oscillation signal,

$\begin{equation} V_{\rm gs3} (t)=V_{\rm B}+A\cos \omega _{\rm o} t, \end{equation}$

(1)

where A is amplitude of switching signal of NM3, which is determined by oscillation amplitude and capacitor ratio, and $\omega _{\rm o}$ is oscillation frequency. Firstly, we assume the tail bias transistor operates in saturation region, and the current dissipation is

$\begin{equation} I_{\rm d3} (t)=\frac{1}{2}\beta [V_{\rm B}+A\cos (\omega _{\rm o} t)-V_{\rm th}]^2, \end{equation}$

(2)

where $\beta =\mu _{\rm n} C_{\rm OX} \frac{W}{L}$. The average current generated in NM3 is derived as

$\begin{equation} \overline {I_{\rm d3} } =\frac{1}{T}\int_0^T {I_{\rm d3} (t){\rm d}t}=\frac{1}{2}\beta (V_{\rm B}-V_{\rm th})^2+\frac{1}{4}\beta A^2. \end{equation}$

(3)

The second term contributes additional current dissipation, thus the total power consumption increases significantly with large switching amplitude A. However, sufficient switching of the tail current transistor between strong inversion and accumulation is useful to reduce intrinsic flicker noise effectively^[5]. Thus trade-off between phase noise and power consumption is the main limitation of self-switched biasing technology.

To get lower power, supply voltage is pulled down, resulting in the tail bias transistor operating in the triode region rather than the saturation region. The current of NM3 in the triode region is given by

$\begin{equation} I'_{\rm d3} (t)=\frac{1}{2}\beta V_{\rm ds3} [2(V_{\rm B}+A\cos (\omega _{\rm o} t)-V_{\rm th} )-V_{\rm ds3}]. \end{equation}$

(4)

In Ref. [6], a long channel transistor in the triode region is modeled by two back-to-back transistors in the saturation region with the same size, as shown in Fig. 5. The current of NM3 in the triode region is given by

$\begin{equation} I'_{\rm d3} (t)=I_{\rm a} (t)-I_{\rm b} (t), \end{equation}$

(5)

where $I_{\rm a} (t)$ and $I_{\rm b} (t)$ are current of transistors in saturation:

$\begin{equation} \begin{split} I_{\rm a} (t){}& =\frac{1}{2}\beta (V_{\rm gs3} -V_{\rm th} )^2 \\& =\frac{1}{2}\beta [V_{\rm B}+A\cos (\omega _{\rm o} t)-V_{\rm th}]^2, \\ \end{split} \end{equation}$

(6)

$\begin{equation} \begin{split} I_{\rm b} (t){}& =\frac{1}{2}\beta (V_{\rm gd3} -V_{\rm th} )^2 \\& =\frac{1}{2}\beta [V_{\rm B}+A\cos (\omega _{\rm o} t)-V_{\rm ds3}-V_{\rm th}]^2. \\ \end{split} \end{equation}$

(7)

The average value of $I_{\rm a}$ is

$\begin{equation} \overline {I_{\rm a}} =\frac{1}{T}\int_0^T {I_{\rm a} (t){\rm d}t} =\frac{1}{2}\beta (V_{\rm B}-V_{\rm th} )^2+\frac{1}{4}\beta A^2. \end{equation}$

(8)

As the variation of $V_{\rm ds3}$ is small when NM3 is in the triode region, and for the sake of simplicity, suppose $V_{\rm ds3}$ is constant, then use its average value $\overline {V_{\rm ds3} }$ to derive the average value of $I_{\rm b}$ as

$\begin{equation} \overline {I_{\rm b}} =\frac{1}{T}\int_0^T {I_{\rm b} (t){\rm d}t} \approx \frac{1}{2}\beta (V_{\rm B}-V_{\rm th} -\overline {V_{\rm ds3} } )^2+\frac{1}{4}\beta A^2. \end{equation}$

(9)

Thus the average current of NM3 in the triode region is

$\begin{equation} \begin{split} \overline {I'_{\rm d3}} {}& =\overline {I_{\rm a} } -\overline {I_{\rm b} } \\& \approx \frac{1}{2}\beta (V_{\rm B}-V_{\rm th} )^2-\frac{1}{2}\beta (VB-V_{\rm th} -\overline {V_{\rm ds3}})^2. \\ \end{split} \end{equation}$

(10)

Although the estimation of Eq. (10) is based on not so strict assumption, the results could help us to inspect the power consumption. Compared to Eq. (3), the current dissipation for triode operation in Eq. (10) does not depend on switching amplitude A, thus power consumption should be reduced. The simulated average current of NM3 in saturation and triode region are illustrated in Fig. 6, where the different switching swing 2A is realized by a different proportion of capacitors, while keeping constant oscillation amplitude and the same oscillation frequency. Obviously, the current in saturation is much larger than that in the triode region, and the strong dependence on switching swing almost vanishes as depicted in Eq. (10).

2.3 Tuning characteristics linearization

Frequency tuning characteristic is another important feature when VCO is used in PLL. The loop gain of PLL will change with the variation of VCO gain, which may deteriorate the stability and phase noise performance of PLL.

VCO gain is given by

$\begin{equation} K_{\rm VCO} =\frac{\partial \omega _{\rm o}}{\partial V_{\rm ctl} }=\frac{\partial \omega _{\rm o} }{\partial C_{\rm var} }\frac{\partial C_{\rm var} }{\partial V_{\rm ctl} }, \end{equation}$

(11)

where $C_{\rm var}$ is capacitance of varactor, $V_{\rm ctl}$ is control voltage, and $\omega_{\rm o}$ is oscillation frequency as

$\begin{equation} \omega _{\rm o} =\frac{1}{\sqrt {L(C_{\rm o} +C_{\rm var} )} }, \end{equation}$

(12)

where L is inductance of tank, and $C_{\rm o}$ is fixed capacitance of tank. Thus VCO gain can be written as

$\begin{equation} K_{\rm VCO} =-\frac{1}{2}\frac{\omega _{\rm o} }{C_{\rm o} +C_{\rm var} }\frac{\partial C_{\rm var} }{\partial V_{\rm ctl} }. \end{equation}$

(13)

Obviously, VCO gain is determined by C-V gain of varactor $\partial C_{\rm var }$/$\partial V_{\rm ctl}$.

Usually, the varactor is biased by a single reference voltage $V_{\rm ref1}$ as shown in Fig. 7(a), and its C-V curve is exhibited in Fig. 7(b). Since the C-V curve of the varactor is linear in limited range $L_{\rm R}$, and flat in rest control voltage range, the VCO gain is non-linear according to Eq. (13) in the whole voltage tuning range.

To solve the problem, distributed varactor biasing^[10] is used in this design. As shown in Fig. 8(a), two single biased varactors of the same size are parallel connected, and biased by different references, $V_{\rm ref1}$ and $V_{\rm ref2}$. The corresponding C-V characteristics are shown in Fig. 8(b), where $C_{1}$ and $C_{2}$ are capacitance of two single biasing varactors, and the total capacitance C is a summation of $C_{1}$ and $C_{2}$. If $V_{\rm ref1}$ and $V_{\rm ref2}$ are set properly, the linear range of the distributed biasing varactor, denoted as LR, will be about the summation of two single biasing range LR1 and LR2. Since the C-V gain of varactor $\partial C_{\rm var}$/$\partial V_{\rm ctl}$ is linear in doubled range for distributed biasing, the resulting frequency tuning characteristic would be linearized in extended voltage control range, with smaller variation of gain, which is confirmed by measurement results shown in Section 4.

3. Measurement results and discussion

To widen the tuning range with small gain, a binary weighted capacitor array is used as in Fig. 9. The proposed VCO is fabricated in SMIC 0.18-$\mu$m CMOS process. Figure 10 shows the micrograph of the fabricated VCO with a chip area of 650 $\mu$m × 510 $\mu$m (excluding pads).

Figure 11 shows the measured frequency tuning characteristics of the proposed oscillator. The tuning range is from 2.38 to 2.61 GHz, which is divided into 8 bands, each with control voltage from 0.1 to 1.1 V. Good linearity of frequency tuning characteristics in each band is achieved by distributed varactor biasing technology as expected. Another beneficial result is the minimized VCO gain. The maximum and minimum gain is 56.5 and 46.6 MHz/V, and the average gain of all bands is 51.4 MHz/V, thus the maximum variation of oscillation gain is less than $\pm$10%.

The phase noise is measured using Agilent signal analyzer N9030A, as shown in Fig. 12, which reach $-77.5$ dBc/Hz, $-97.5$ dBc/Hz and $-122.8$ dBc/Hz at 10 kHz, 100 kHz and 1 MHz offset, respectively, while consuming current of 2.7 mA at a supply voltage of 1.2 V. Elimination of $1/f^3$ dependency of close-in phase noise proves the reduction of flicker noise. The measured frequency range, phase noise and power dissipation well fit the project requirements as mentioned in Section 1.

The commonly used figure of merit (FoM) is defined as

$\begin{equation} {\rm FoM}=20\lg \frac{f_{\rm o}}{\Delta f}-10\lg \frac{P}{\rm 1mW}-{\rm PN}, \end{equation}$

(14)

where $f_{\rm o}$ is the oscillation frequency, $\Delta f$ is the offset frequency, P is power dissipation in mW, and PN is the phase noise in dBc/Hz. The proposed oscillator gets FoM of 186 dBc/Hz at 1 MHz offset. The main results are compared with relative work in Table 1, which are all implemented in 0.18 μm technology. Self-switched biasing is used in Ref. [5] for QVCO, which achieves surprisingly low phase noise with the penalty of huge power consumption, while our design reduced power consumption significantly by triode region biased tail transistors. Reference [11] presented optimization of phase noise and power consumption for differential output by setting the differential pair to operating at the boundary between the saturation and triode regions, while Reference [12] adopted current reusing VCO and divider for quadrature output; however, their improvement of FoM is limited by the quality factor of the LC tank, which determines phase noise and power if without additional effective technology. Colpitts VCO in Ref. [13] achieved the highest FoM for low phase noise and low power consumption, but to meet the rigorous start-up condition of Colpitts VCO, additional boosted circuits are needed. VCO with enhanced quality factor and linearized C-V curve of varactors for wide frequency range^[14] is also compared. Compared to other works, our design exhibits low phase noise with low power dissipation by proposed technology, thus achieving higher FoM than other works except^[13]. Additionally, our chip occupies a small area, only larger than Ref. [11] in table.

4. Conclusion

A 2.38 to 2.61 GHz differential VCO is presented, whose low phase noise, low power and linearized frequency tuning characteristics are achieved by design optimizations with effective techniques. The improved performance makes the proposed VCO fit for the requirements of our Zigbee transceiver.