1. Introduction

With the rapid development of global navigation satellite systems, built-in navigation and positioning functions are becoming standard features for cellular handsets and other low-cost embedded applications^[1]. To match the high precision positioning requirement with very weak satellite signals such as in indoor applications, the GNSS receiver should have high receiving sensitivity. As the first active circuit module of the receiver's RF front end, the LNA is required to give an ultra-low noise figure and high power gain.

Low noise devices based on Si RFCMOS, SiGe HBT and GaAs pHEMT are among the most popular for LNA research^[2-4]. Si RFCMOS LNAs have good integration and cost advantages, and have been used in SOC receivers^[5]. GaAs pHEMT LNAs exhibit excellent noise and high frequency performances. SiGe HBTs combine the advantages of the former two types^{[6, 7]}, especially in designing L-band LNAs.

In this paper, a SiGe BiCMOS process based LNA for GNSS receivers is described, which reaches a sub-1-dB noise figure under very limited power and area consumption. The LNA also has a simple impedance matching circuit with only one off-chip inductor needed to offer excellent input/output impedance matching. The second section describes the analysis and design of the LNA. The third section introduces the implementation and measurement results of the LNA. The last section provides the conclusion.

2. LNA analysis and design

2.1 Noise and input impedance matching

Figure 1(a) shows the topology of the cascode LNA. Q0 is the common emitter (CE) stage and Q1 the common base (CB) stage, which consists of parallel HBT transistors. $Z_{\rm L}$ is the load of the LNA. $L_{\rm e}$ and $L_{\rm b}$ are respectively the on-chip spiral inductor and off-chip high-Q inductor. $L_{\rm bw}$ is the parasitic inductor of the bonding wire. Two pads and also two bonding wires are applied to the GND port to reduce the parasitic inductance. $C_{\rm p0}$ represents the parasitic capacitance of ESD devices, pads and package at the input node. $C_{\rm pb}$ represents parasitic capacitance along the input signal line on the printed circuit board (PCB). Figure 1(b) is the simplified small signal equivalent circuit ignoring the cascade stage, where $C_{\rm p}$ = $C_{\rm pb}$ $+$ $C_{\rm p0}$, $C_{\pi}$ is the base-emitter capacitance of Q0, $r_{\rm b}$ and $r_{\rm e}$ are respectively the base and emitter serial resistor, $r_{\rm lb}$ is the serial resistor of $L_{\rm b}$, $R_{\rm L}$ = Re[$Z_{\rm L}$] is the load resistor and $g_{\rm m}$ is the transconductance of Q0. Applying a 2-port network analysis method, the noise figure of the LNA can be described as

$\begin{equation} {\rm NF}={\rm NF}_{\rm min} +\frac{R_{\rm n}}{G_{\rm s}}\left( {Y_{\rm s} -Y_{\rm s, \, opt} } \right)^2, \end{equation}$

(1)

where NF$_{\rm min}$ is the minimum noise figure, $Y_{\rm s}$ the source admittance, $G_{\rm s}$ = 1/$R_{\rm s}$ the source conductance, $Y_{\rm s, \, opt}$ the noise matching source admittance, $G_{\rm s, \, opt}$ and $B_{\rm s, \, opt}$ are the real and imaginary parts respectively of $Y_{\rm s, \, opt}$, and $R_{\rm n}$ the noise resistance. Ignoring the contribution from the CB stage, 2-port noise parameters can be derived from the noise figure^[8].

$\begin{equation} {\rm NF}_{\rm min} =1+2\sqrt {U V}, \end{equation}$

(2)

$\begin{equation} R_{\rm n} =U, \end{equation}$

(3)

$\begin{equation} G_{\rm s, opt} =\sqrt{V/U}, \end{equation}$

(4)

$\begin{equation} \begin{split} {}& U=r_{\rm lb} +\left[r_{\rm x} +\frac{1}{2\beta g_{\rm m}}\left(\frac{\omega _{\rm T}}{\omega _0 }\right)^2\right] k^2, \\& V=\left[\frac{g_{\rm m}}{2\beta }+\frac{g_{\rm m}}{2\left( {{\omega _{\rm T}}/{\omega _0 }} \right)^2}+\frac{4}{R_{\rm L} \left( {{\omega _{\rm T} }/{\omega _0 }} \right)^2}\right] \frac{1}{k^2}, \\ \end{split} \end{equation}$

(5)

where $k=C_{\pi }$/($C_{\pi }$ $+$ $C_{\rm p})$, $r_{\rm x}$ = $r_{\rm b}$ $+$ $r_{\rm e}$, $\omega_{0}$ is the center frequency, $\omega_{\rm T}$ the unit current gain frequency of the SiGe HBT. To obtain an ultra-low noise figure, several optimizing steps should be followed. Firstly, get minimum NF$_{\rm min}$. HBT transistors are the main noise contributors to the minimum noise figure of the LNA. The minimum noise figure of an HBT transistor NF$_{\rm min-HBT}$ depends on current gain $\beta$, transconductance $g_{\rm m}$ and $\omega_{\rm T}$^[9] and these parameters all have a strong correlation with emitter current density $J_{\rm c}$. In this way, it is reasonable to hypothesize that NF$_{\rm min-HBT}$ is approximately a function of $J_{\rm c}$. The curve of NF$_{\rm min-HBT}$ at $\omega_0$ can be achieved by sweeping $J_{\rm c}$. As shown in Fig. 2, the minimum NF$_{\rm min-HBT}$ of 430.2 mdB can be obtained when $J_{\rm c, \, opt}$ equals about 100 μA/$\mu$m². The unit current gain $\omega_{\rm T}$ is about 16 GHz at this point. The noise contribution of $r_{\rm lb}$ increases to $1/k$ times of the primary because of $C_{\rm p}$. So, the ESD, pad and layout should be carefully treated to cut down $C_{\rm p}$ and a high-Q off-chip inductor should be used. Secondly, noise matching namely $G_{\rm s, \, opt}$ = $G_{\rm s}$, $B_{\rm s, \, opt}$ = 0 should be achieved in the design. 1/$G_{\rm s, \, opt}$ of an HBT transistor (emitter area is 0.2 × 4 $\mu$m²) is about several k$\Omega$ which means tens of parallel transistors should be used to increasing $G_{\rm s, \, opt}$ to $G_{\rm s}$. The optimum number of parallel HBTs $N_{\rm opt}$ is 36 as Figure 3 illustrates. At this point, $R_{\rm s, \, opt}$ $\approx$ 50 $\Omega$ = $R_{\rm s}$, and the collector current is about 2.88 mA. Thirdly, noise resistance $R_{\rm n}$ needs to be optimized. High $\beta$ HBT should be chosen and multi-finger technology should be used in the layout design.

After obtaining $J_{\rm c, \, opt}$ and $N_{\rm opt}$, passive elements for input impedance matching are determined. For the LNA shown in Fig. 1(a), the input impedance is

$\begin{equation} \begin{split} Z_{\rm in} \approx {}& {\rm j}\omega _0 \left( {L_{\rm b} +L_{\rm e} +\frac{3}{2}L_{\rm bw} } \right)+\frac{1}{{\rm j}\omega _0 (C_\pi +C_{\rm pb} +C_{\rm p0} )} \\& +\omega _{\rm T} (L_{\rm e} +\frac{L_{\rm bw} }{2})k^2. \end{split} \end{equation}$

(6)

Using input impedance matching conditions, then

$\begin{equation} Z_{\rm in} =\omega _{\rm T} \left(L_{\rm e} +\frac{1}{2}L_{\rm bw} \right)k^2=R_{\rm s}. \end{equation}$

(7)

As $C_{\rm pb}$ has a significant effect on input impedance.^[8], this parasitic capacitance should be evaluated during the early design phase. The estimated value of $C_{\rm pb}$ can be obtained by comparing the simulated and measured $S_{11}$ in a Smith chart (namely points A and B in Fig. 4(a)). Precise input impedance matching is reached by adding $C_{\rm pb}$ into the design equation. The equivalent transconductance of the LNA can be derived from the analysis of the small signal equivalent circuit in Fig.1(b).

$\begin{equation} \begin{split} G_{\rm m} ={}& g_{\rm m} \left\{\left[{1-\omega _0 ^2C_{\rm p} (L_{\rm b} +L_{\rm bw} )} \right] \left[1+{\rm j}\omega (L_{\rm e} +0.5L_{\rm bw} )\right.\right. \\& \left.\left. -\omega ^2C_\pi (L_{\rm e} +0.5L_{\rm bw} ) \right]-\omega _0 ^2C_\pi \left( {L_{\rm b} +L_{\rm bw} } \right)\right\}^{-1}. \end{split} \end{equation}$

(8)

Under the condition of input impedance matching and $\omega_{0}^{2}$$C_{\pi }$($L_{\rm e}$ $+$ 0.5$L_{\rm bw})$ $\ll$ 1, the equivalent transconductance is expressed as

$\begin{equation} G_{\rm m} \approx \frac{1}{k} \frac{1}{{\rm j}\omega _0 (L_{\rm e} +0.5L_{\rm bw} )}. \end{equation}$

(9)

In this design, $C_{\rm pb}$ $\approx$ 300 fF, $C_{\rm p0}$ $\approx$ 200 fF and $C_{\pi }$ $\approx$ 800 fF which leads to k = 8/13. Substitute $L_{\rm bw}$ $\approx$ 1 nH into Eq. (7), and $L_{\rm e}$ can be derived to be 0.42 nH. And $L_{\rm b}$ is 5.8 nH to satisfy the matching condition Im[$Z_{\rm in}$] = 0.

2.2 Output impedance matching and power gain

Figure 5(a) illustrates the LC network and output impedance matching circuit of the LNA. $L_{\rm c}$ is the on-chip spiral inductor. $C_{\rm m}$ is the MiM capacity for output impedance matching. $C_{\rm c}$ is the MiM capacity and parasitic capacitance at the collector of Q1. Applying serial-parallel transformation to $C_{\rm m}$ and $R_{\rm s}$ as shown in Fig. 5(b), then we have $C_{\rm mp}$ = $C_{\rm m}$/[1$+$($\omega_{0}$$C_{\rm m}$$R_{\rm s})^{2}]$ and $R_{\rm sp}$ = $R_{\rm s}$[1$+$1/($\omega_{0}$$C_{\rm m}$$R_{\rm s})^{2}]$ where $R_{\rm lp}$ = $\omega_{0}$$L_{\rm c}$$Q_{\rm l}$ is the equivalent parallel parasitic resistance. The LC network resonates at the frequency of $\omega_{0}$ and matches the load resistor $R_{\rm s}$, then

$\begin{equation} \omega _0^2 L_{\rm c} (C_{\rm mp} +C_{\rm c} )=1, \end{equation}$

(10)

$\begin{equation} R_{\rm sp} =R_{\rm lp} . \end{equation}$

(11)

Solve Eqs. (10) and (11), then

$\begin{equation} \begin{cases} C_{\rm m} \approx \dfrac{1+\sqrt {1+4Q_{\rm l} \omega _0 R_{\rm s} C_{\rm c}} }{2Q_{\rm l} \omega _0 R_{\rm s}}, \\ L_{\rm c} \approx \dfrac{R_{\rm s}}{\omega _0 Q_{\rm l}} \left[{1+\left( {\dfrac{2Q_{\rm l}}{1+\sqrt {1+4Q_{\rm l} \omega _0 R_{\rm s} C_{\rm c}} }} \right)^2} \right]. \end{cases} \end{equation}$

(12)

It is suggested that properly choosing the value of $C_{\rm c}$ is important from observing Eq. (12). If $C_{\rm c}$ is very small, then $C_{\rm m}$ $\approx$1/($Q_{\rm l}$$\omega_{0}$$R_{\rm s})$ and $L_{\rm c}$ $\approx$ $R_{\rm s}$$Q_{\rm l}$/$\omega_{0}$ which implies large $L_{\rm c}$ and also large area occupation. If $C_{\rm c}$ is large, small $L_{\rm c}$ as well as low power gain can be derived since the power gain of the LNA under the input and output impedance matching conditions is

$\begin{equation} G_{\rm T} =\frac{\left( {G_{\rm m} R_{\rm L} } \right)^2R_{\rm s} }{R_{\rm sp} }\approx \frac{\omega _{\rm T} }{\omega _0 }\frac{L_{\rm c} }{L_{\rm e} +0.5L_{\rm bw}} \frac{Q_{\rm l}}{4}, \end{equation}$

(13)

where $R_{\rm L}$ = $R_{\rm lp}$ $\vert$$\vert$$R_{\rm sp}$ = 1/(2$R_{\rm lp})$ is the load resistance. In this design, power gain is set to be 22 dB with some redundancy according to the design target of 20 dB. Substituting $\omega_{\rm T}$ = 2$\pi$ × 16 GHz, $\omega _{0}$ = 2$\pi$ × 1.575 GHz, $L_{\rm e}$ $+$ 0.5$L_{\rm bw}$ = 0.92 nH, $Q_{\rm l}$ = 8 into Eq. (13), we get $L_{\rm c}$ = 7.2 nH. Then $C_{\rm c}$ and $C_{\rm m}$ are calculated be to 0.74 pF and 0.57 pF respectively.

3. Implementation and measurement

From the analysis of the LNA, the main design parameters were calculated and then optimized under trade-offs between noise figure, power gain, linearity, power consumption and so on as listed in Table 1. The optimum $L_{\rm c}$ is larger than the calculated one. Parasitic effects decrease Q of $L_{\rm c}$. So, larger $L_{\rm c}$ is needed to obtain the required power gain according to Eq. (13). Only about 1/3 of the calculated $C_{\rm c}$ is needed since the parasitic capacitance at the collector node of Q1 is relatively large.

The LNA was implemented based on a 0.18 μm SiGe BiCMOS process with area occupation of 600 × 650 $\mu$m². The die photograph is shown in Fig. 6. There are six pads with the RFIN and RFOUT pads lying along the two long sides respectively for better inverse isolation and stability. A digitally controlled SHDN port is also integrated. The fabricated LNA was mounted to a small 6-pin package to ease parasitic effects. And then the packaged LNA was tested on PCB board.

The S parameters were measured with the help of an Agilent E5062A network analyzer. Figure 7 shows the measured S parameters with $S_{11}$ better than -12.7 dB, $S_{22}$ better than -20.2 dB, $S_{21}$ better than 18.6 dB and $S_{12}$ better than -31.2 dB at the frequency of 1575 MHz. The noise figure was measured with the help of an Agilent N9020A signal analyzer and an Agilent N4000A noise source. As illustrated in Fig. 8, a flat noise figure curve from 1.570 to 1.580 GHz is achieved and the average NF at 1575 MHz is about 0.97 dB even with the loss of connectors. The linearity performance was measured with the help of an Agilent E4438C vector signal generator and the signal analyzer mentioned above. By using 2-tone measuring method with 2 tones at 1570 MHz and 1565 MHz respectively, the measured IIP3 is about $-6$ dBm as illustrated in Fig. 9.

Table 2 shows a comparison of the LNA with other SiGe HBT LNAs. The proposed LNA exhibits a state-of-art noise figure thanks to the excellent noise matching and optimization. Comparing to Refs. [1, 11], some power gain and linearity are sacrificed respectively to achieve low power consumption. Significant advantages over Ref. [4] are mainly due to the simpler architecture and more advanced process adopted.

4. Conclusions

In this paper, an L band LNA for GNSS application is designed. By taking the input node's parasitic capacitance into consideration and proposing a design method of monolithically designing the LC load and the output impedance matching circuit, the LNA simultaneously gives precise input/output impedance matching and noise matching. Fabricated with a 0.18 μm SiGe BiCMOS process, the die occupies an area of 0.39 $\mu$m². The measurement results exhibit that a 0.97 dB noise figure, 18.6 dB power gain, and $-6$ dBm IIP3 are achieved with only 5.4 mW power consumed from a 1.8 V voltage source.