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J. Semicond. > 2013, Volume 34 > Issue 9 > 095012
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SEMICONDUCTOR INTEGRATED CIRCUITS

A dual redundancy radiation-hardened flip-flop based on a C-element in a 65 nm process

Gang Chen1, 2, Bo Gao1, 2 and Min Gong1, 2,

+ Author Affiliations

 Corresponding author: Gong Min, Email:mgong@scu.edu.cn

DOI: 10.1088/1674-4926/34/9/095012

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Abstract: A radiation-hardened flip-flop is proposed to mitigate the single event upset (SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop.

Key words: single event effect, radiation hardening by design, triple modular redundancy flip-flop, C-element

With the rapid evolution of semiconductor laser technology, the optical power of laser diodes (LDs) keeps increasing, and the joule heat induced by series resistance increases. The joule heat needs to be dissipated effectively otherwise will adversely affect LD performance and reliability[1]. Therefore, packaging techniques with a low thermal resistance are needed. The total thermal resistance of LD packaging is limited by the portion with the highest thermal resistance. The solder layer, which bonds LD chips and heat sinks, is the portion with lowest thermal conductivity in the GaN-based LD package. Therefore, it has a significant effect on the total thermal resistance[2]. To improve the optical power, decreasing the thermal resistance of the bonding layer is effective[3, 4].

As the material connecting the LD chips and the heat sink, solder plays an important role in the thermal packaging system. Au80Sn20 alloy has good thermal and electrical conductivity. As a hard solder with high melting point, Au80Sn20 alloy has good creep resistance and mechanical properties, and thus it can be used in LDs, power electronics, MEMS sensors, and other applications[5-8]. Due to the big difference of electronegativity between Au (2.3) and Sn (1.8), Au80Sn20 alloy tends to form a stable intermetallic compound (IMC) rather than solid solution. The IMCs in Au80Sn20 alloy play a key role in the mechanical and thermoelectric properties[9, 10].

In this paper, the thermal resistance of GaN-based blue laser diodes packaged in TO56 cans were measured by the forward voltage method. The microstructures of Au80Sn20 solder were then investigated to understand the reason for the difference in thermal resistance. It was found that the microstructure with higher content of Au-rich phase in the center of the solder and lower content of (Au,Ni)Sn phase at the interface of the solder/heat sink resulted in lower thermal resistance.

The packaged LD samples studied here are from the same epitaxial wafer and chip processing but different packaging processing, and the chip size of both is 200 × 400 μm2. The results shown in this paper are from typical samples of each batch named E09 and Y00. These two samples have a similar structure, and the schematic diagram of the structure is shown in Fig. 1. The Au80Sn20 solder bonds the LD chip and heat sink, and there are two solder layer interfaces.

Figure  1.  The schematic diagram of structure of packaged laser diodes.
DownLoad: Full-Size Img PowerPoint

We first measured the thermal resistance of TO56 packaged GaN-based LDs using the forward voltage method, which was reported by us previously[11]. It is based on the linear relation between the junction temperature (T) and the forward voltage (Vf). When the injection current is a constant[12-15], the relation can be fitted as follows:

Vf=AT+B, (1)

where T is the junction temperature of the LD, and A and B are the fitting parameters. We first measured the value of the temperature-sensitive parameter A. Next, by changing the injection current from an operation current to a very low current at which joule heat is negligible, we measured the voltage variation (ΔV) of the LD caused by the variation of the junction temperature (ΔT) using a MDO4104-3 mixed domain oscilloscope. The ΔT can be calculated by the following equation:

ΔT=(Vf0−Vft)/A, (2)

where Vft is the forward voltage of the LD at high injected current. As the joule heat dissipates rapidly, the decrease of junction temperature will cause the forward voltage to increase[16]. Vf0 is the forward voltage of the LD when the junction temperature decreases to room temperature. The thermal resistance (Rth) of the LD can be expressed as[15]:

Rth=ΔTJ/(IHVH−Popt), (3)

where IH is the injection current, while VH and Popt are the voltage and optical output power of the LD under the corresponding injection current IH.

For IMCs analysis, the scanning electron microscope (SEM) and energy dispersive X-ray spectroscopy (EDS) have been carried out. We selected FEI quanta FEG 250 to perform SEM, which has EDS subassembly named EDXX Apollo XP. In order to observe the IMCs in the solder joint clearly, the packaged LDs were polished into cross-sectional samples.

Fig. 2 shows the power–current (P–I) curves of two LD samples. E09 has a lower threshold current and a higher slope efficiency than Y00. It is suggested that the difference of optical power between these two LD samples is caused by the different thermal resistance.

Figure  2.  (Color online) The P–I curve of sample E09 and Y00.
DownLoad: Full-Size Img PowerPoint

In order to verify the effect of thermal resistance on optical power, we then measured the thermal resistance of the two samples. From the I–V curves under different measured temperatures, the relation between the junction temperature and the forward voltage was fitted with Eq. (1), and the temperature-sensitive parameter A was thus calculated to be 4.33 mV/K for E09, 2.66 mV/K for Y00. We then measured the time-resolved voltage variation of these two samples. In the working state, after the LD samples reached a steady-state, we measured the working current IH, voltage VH and optical output power Popt. In the measuring state, we measured the variation of forward voltage from the very beginning of the measuring state to room temperature. According to our previous simulation and experimental work[11, 17], the time-resolved voltage curve of a LD can be distinguished by the slope and the time scale. When the current injected into a LD was reduced to a very low value, the heat generated in the LD chip dissipated to the heat sink. During this process, the temperature at different positions of the LD change over different time scale and different rate. The time scale of the heat dissipation of a LD chip and solder junction were 0–10–4 s and 10–4–0.1 s, respectively. Fig. 3 shows the first two periods of the voltage variation with time. The first period is caused by heat dissipation in the LD chip, and the second period is caused by heat dissipation in the solder layer.

Figure  3.  (Color online) The time-resolved voltage variation during the measurement.
DownLoad: Full-Size Img PowerPoint

The voltage variation of the solder layer (Vf0–Vft) is 85.37 mV for E09 and 59.05 mV for Y00. Table 1 shows all the parameters of thermal resistance calculation. According to Eqs. (2) and (3), the thermal resistance was 41.95 K/W for E09 and 65.29 K/W for Y00. The total thermal resistance of a LD is determined by chip structure, bonding materials and microstructure, and heat sink. In our study, the chip structure, the heat sink, and the bonding materials are the same, and therefore we focused on the microstructure of the solder layer, as follows.

Table  1.  Parameters of thermal resistance calculation.
SampleA (mV/K)Vf0–Vft (mV)IHVH–Popt (W)Rth (K/W)
EL-004.3385.370.4741.95
YJ-092.6659.050.3465.29
DownLoad: CSV  | Show Table

The gold-rich portion of the Au–Sn phase diagram is shown in Fig. 4[18]. The IMC phases of interest in solder are β(Au10Sn), ζ’(Au5Sn) phase, ζ(Au5Sn)phase and δ(AuSn) phase. From the phase diagram, the Au80Sn20 alloy system consists of ζ’ phase and δ phase at room temperature. In practice, however, the nonequilibrium solidification usually results in the formation of primary ζ phase. In addition, Teo et al. have also found β phase in Au80Sn20 solder joint[19]. The eutectic point at 280 °C and 29.0 at.% Sn has the reaction L ↔ [ζ + δ]. There is a peritectoid reaction at 190 °C and 16.0 at.% Sn, ζ’ ↔ [ζ + δ]. Prior to this reaction, it is believed that the reaction at 190°C and 18.5 at. % Sn is ζ ↔ [ζ’ + δ]. The ζ-Au5Sn phase emerges from the peritectic ζ↔[β + L] 9.1 at.% Sn at 521 °C to 17.6 at.% Sn at 280 °C, and 13.9 at.% Sn at 190 °C. The composition of Sn in the hexagonal structure ζ’ phase is 16%, where it remains until the temperature reaches 190 °C. The ζ phase has a Mg-type close-packed hexagonal structure. As the Sn concentration increases, the volume of ζ phase per atom will increase. The δ (AuSn) phase is a hexagonal structure intermetallic compound with a melting point of 419.3 °C. The β phase is considered as a kind of commercial gold solder which is used as Au-protected surfaces[20–22].

Figure  4.  Gold-rich portion of the Au–Sn phase diagram.
DownLoad: Full-Size Img PowerPoint

Fig. 5 shows the cross-sectional SEM images of the solder layer in these two samples. The EDS results and the possible phase of the marked points are shown in Table 2. The thickness of solder layer is roughly 4 μm. The a1, a2, b1, b2 points are at the LD chip/solder interface region. From the EDS results, it can be found that the δ phase is in the same region. Because Sn-rich phase such as δ has a lower surface tension than Au-rich phase, δ phase tends to coalesce at the surface[23, 24]. During the packaging process, Pt diffused from the LD electrode and coalesced at the LD chip/solder interface. As the EDS data shows, there is Pt–Sn phase in the region around points a1, a2. Also, the solder/heat sink interface has an analogous phenomenon. Under the effect of thermal diffusion, Ni in the heat sink coalesced at the solder/heat sink interface. In these regions, Ni replaced Au in AuSn phase to form (Au,Ni)Sn phase[25]. The gray line on the left part of the interfacial layer at the bottom side of E09 is void, which could be induced during the SEM sample preparation. In the center of the solder layer, the bright phase is Au-rich, and the dark phase is Sn-rich. It is notable that most of the Sn-rich phase in sample E09 distributes in the form of spheroidized structure. On the other hand, most of the Sn-rich phase in sample Y00 is lamellar structure. The hard and brittle nature of the primary ζ’ phase which has a dendrite microstructure leads to difficulties in the manufacture of Au80Sn20 solder. According to the phase diagram, Au80Sn20 alloy consists of ζ’ phase and δ phase at room temperature. The reason for the difference of morphology between two samples may be the different cooling rate. At a fast cooling rate, the dendrite growth of ζ’ phase will be suppressed. Furthermore, the suppressed growth results in refined microstructure and metastable phases. At the same time, the dendrites of ζ’ phase will generate more fractions. A mass of branches from the fractions are intertwined. The intertwining process divided the lamellar Sn-rich phase into a spheroidized structure. This structure transformation has a good effect on the mechanical properties of the solder[26].

Table  2.  EDS results of the points marked in Fig. 5.
Parametera b c d f
a1a2 b1b2 c1c2 d1d2 f1f2
Phase(Au,Pt)Sn(Au,Pt)Sn AuSnAuSn AuSnAuSn Au5SnAu5Sn (Au,Ni)Sn(Au,Ni)Sn
at%Au47.446.88 67.2560.11 79.7376.86 87.2781.97 41.1336.03
at%Sn46.6947.01 32.7539.89 20.2723.14 12.7318.03 40.4933.71
at%Pt5.916.11 —— —— —— ——
at%Ni—— —— —— —— 18.3830.26
DownLoad: CSV  | Show Table
Figure  5.  Cross-sectional SEM of the two samples. The red crosses are the EDS measure points.
DownLoad: Full-Size Img PowerPoint

It is suggested that the main reason for the higher thermal resistance in sample Y00 is the lower content of the Au-rich phase. Au-rich phases in the center are the primary phase ζ’ and metastable phase. The Au-rich phase not only has a good mechanical property, but also has a lower thermal resistance. As the content of Au-rich phase in E09 is much higher than that in Y00, E09 has a lower thermal resistance. In addition, the interface also has a great effect on thermal resistance. In this case, the LD/solder interfaces of the two samples are analogous to some extent. However, the content of Ni in the solder/heat sink interface has a remarkable difference. It is believed that Ni comes from the heat sink by thermal diffusion. Since (Au,Ni)Sn is harmful to thermal resistance improvement, the decrease of (Au,Ni)Sn phase in E09 ensures a good thermal contact[27, 28].

In summary, the thermal resistance of GaN-based blue laser diodes packaged in TO56 cans were measured by the forward voltage method. The microstructures of Au80Sn20 solder were then investigated to understand the reason for the difference in thermal resistance. It was found that the microstructure with higher content of Au-rich phase in the center of solder and lower content of (Au,Ni)Sn phase at the interface of the solder/heat sink resulted in lower thermal resistance. This finding will help improve the packaging processing in the future.

This work was supported by the National Key Research and Development Program of China (Grant Nos. 2016YFB0401803, 2017YFE0131500, 2017YFB0405000), National Natural Science Foundation of China (Grant Nos. 61834008, 61574160, 61804164, and 61704184), Natural Science Foundation of Jiangsu province (BK20180254), China Postdoctoral Science Foundation (2018M630619).



[1]
Nicolaidis M. Design for soft error mitigation. IEEE Trans Device Mater Reliab, 2005, 5(3):405 doi: 10.1109/TDMR.2005.855790
[2]
Dodd P E, Shaneyfelt M R, Schwank J R, et al. Current and future challenges in radiation effects on CMOS electronics. IEEE Trans Nucl Sci, 2010, 57(4):1747 doi: 10.1109/TNS.2010.2042613
[3]
Mavis D, Alexander D. Employing radiation hardness by design techniques with commercial integrated circuit processes. AIAA/IEEE 16th Digital Avionics Systems Conference, 1997, 1:2.1 http://ieeexplore.ieee.org/document/635027/authors
[4]
She X, Samudrala P. Selective triple modular redundancy for single event upset (SEU) mitigation. NASA/ESA Conference on Adaptive Hardware and Systems, 2009:344 http://dl.acm.org/citation.cfm?id=1673216
[5]
She X, McElvain K S. Time multiplexed triple modular redundancy for single event upset mitigation. IEEE Trans Nucl Sci, 2009, 56(4):2443 doi: 10.1109/TNS.2009.2021656
[6]
Wang X. Partitioning triple modular redundancy for single event upset mitigation in FPGA. International Conference on E-Product E-Service and E-Entertainment (ICEEE), 2010, 1:7 http://ieeexplore.ieee.org/document/5660842/authors
[7]
Oliveira R, Jagirdar A, Chakraborty T J. A TMR scheme for SEU mitigation in scan flip-flops. Proc 8th Int Symp Quality Electronic Design, 2007:905 http://ieeexplore.ieee.org/document/4149148/
[8]
Golshan S, Bozorgzadeh E. SEU-aware resource binding for modular redundancy based designs on FPGAs. Design, Automation & Test in Europe Conference & Exhibition, 2009:1124 http://dl.acm.org/citation.cfm?id=1874892&dl=ACM&coll=DL&CFID=988920426&CFTOKEN=93551803
[9]
Rennie D J, Sachdev M. Novel soft error robust flip-flops in 65 nm CMOS. IEEE Trans Nucl Sci, 2011, 58(5):2470 doi: 10.1109/TNS.2011.2162745
[10]
Mitra S, Ming Z, Waqas S, et al. Combinational logic soft error correction. Proc International Test Conference, 2006:1
[11]
Fazeli M, Patooghy A, Miremadi S G, et al. Feed-back redundancy:a power efficient SEU-tolerant latch design for deep sub-micron technologies. Proc 37th Annu IEEE/IFIP Int Conf Depend Syst Netw, 2007:276
[12]
Huang Zhengfeng, Liang Huaguo. A novel radiation hardened by design latch. Journal of Semiconductors, 2009, 30(3):035007 doi: 10.1088/1674-4926/30/3/035007
[13]
Wu Lihua, Han Xiaowei, Zhao Yan, et al. Design and implementation of a programming circuit in radiation-hardened FPGA. Journal of Semiconductors, 2011, 32(8):085012 doi: 10.1088/1674-4926/32/8/085012
Fig. 1.  The cross-sectional view of an inverter with its parasitic latch-up structure shown. High energy particle striking the drains of the inverter creates a transient in the logic path

DownLoad: Full-Size Img PowerPoint
Fig. 2.  A triple modular redundancy (TMR) flip-flop

DownLoad: Full-Size Img PowerPoint
Fig. 3.  A C-element based SEU resilient latch proposed in Ref. [11]

DownLoad: Full-Size Img PowerPoint
Fig. 4.  The proposed SEU resilient flip-flop. Two identical data paths are cross-coupled by C-elements

DownLoad: Full-Size Img PowerPoint
Fig. 5.  Simulation waveforms of the internal nodes and the output of the proposed SEU resilient flip-flop

DownLoad: Full-Size Img PowerPoint
Fig. 6.  The layout of the proposed flip-flop, sensitive nodes locate at the opposite side. The flip-flop occupies an area of 27 μm2

DownLoad: Full-Size Img PowerPoint
Fig. 7.  A pilot chip carries the proposed flip-flop and other testing structures, implemented using a Global Foundries 65 nm CMOS process

DownLoad: Full-Size Img PowerPoint

Table 1.   Implementation results of the proposed flip-flop
[1]
Nicolaidis M. Design for soft error mitigation. IEEE Trans Device Mater Reliab, 2005, 5(3):405 doi: 10.1109/TDMR.2005.855790
[2]
Dodd P E, Shaneyfelt M R, Schwank J R, et al. Current and future challenges in radiation effects on CMOS electronics. IEEE Trans Nucl Sci, 2010, 57(4):1747 doi: 10.1109/TNS.2010.2042613
[3]
Mavis D, Alexander D. Employing radiation hardness by design techniques with commercial integrated circuit processes. AIAA/IEEE 16th Digital Avionics Systems Conference, 1997, 1:2.1 http://ieeexplore.ieee.org/document/635027/authors
[4]
She X, Samudrala P. Selective triple modular redundancy for single event upset (SEU) mitigation. NASA/ESA Conference on Adaptive Hardware and Systems, 2009:344 http://dl.acm.org/citation.cfm?id=1673216
[5]
She X, McElvain K S. Time multiplexed triple modular redundancy for single event upset mitigation. IEEE Trans Nucl Sci, 2009, 56(4):2443 doi: 10.1109/TNS.2009.2021656
[6]
Wang X. Partitioning triple modular redundancy for single event upset mitigation in FPGA. International Conference on E-Product E-Service and E-Entertainment (ICEEE), 2010, 1:7 http://ieeexplore.ieee.org/document/5660842/authors
[7]
Oliveira R, Jagirdar A, Chakraborty T J. A TMR scheme for SEU mitigation in scan flip-flops. Proc 8th Int Symp Quality Electronic Design, 2007:905 http://ieeexplore.ieee.org/document/4149148/
[8]
Golshan S, Bozorgzadeh E. SEU-aware resource binding for modular redundancy based designs on FPGAs. Design, Automation & Test in Europe Conference & Exhibition, 2009:1124 http://dl.acm.org/citation.cfm?id=1874892&dl=ACM&coll=DL&CFID=988920426&CFTOKEN=93551803
[9]
Rennie D J, Sachdev M. Novel soft error robust flip-flops in 65 nm CMOS. IEEE Trans Nucl Sci, 2011, 58(5):2470 doi: 10.1109/TNS.2011.2162745
[10]
Mitra S, Ming Z, Waqas S, et al. Combinational logic soft error correction. Proc International Test Conference, 2006:1
[11]
Fazeli M, Patooghy A, Miremadi S G, et al. Feed-back redundancy:a power efficient SEU-tolerant latch design for deep sub-micron technologies. Proc 37th Annu IEEE/IFIP Int Conf Depend Syst Netw, 2007:276
[12]
Huang Zhengfeng, Liang Huaguo. A novel radiation hardened by design latch. Journal of Semiconductors, 2009, 30(3):035007 doi: 10.1088/1674-4926/30/3/035007
[13]
Wu Lihua, Han Xiaowei, Zhao Yan, et al. Design and implementation of a programming circuit in radiation-hardened FPGA. Journal of Semiconductors, 2011, 32(8):085012 doi: 10.1088/1674-4926/32/8/085012
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    Hao Lin, Deyao Li, Liqun Zhang, Pengyan Wen, Shuming Zhang, Jianping Liu, Hui Yang. Effect of microstructure of Au80Sn20 solder on the thermal resistance TO56 packaged GaN-based laser diodes[J]. Journal of Semiconductors, 2020, 41(10): 102104. doi: 10.1088/1674-4926/41/10/102104
    H Lin, D Y Li, L Q Zhang, P Y Wen, S M Zhang, J P Liu, H Yang, Effect of microstructure of Au80Sn20 solder on the thermal resistance TO56 packaged GaN-based laser diodes[J]. J. Semicond., 2020, 41(10): 102104. doi: 10.1088/1674-4926/41/10/102104.
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    Received: 16 January 2013 Revised: 25 March 2013 Online: Published: 01 September 2013

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      Article Navigation >  Journal of Semiconductors  > 2013  >  34(9): 095012
      Hao Lin, Deyao Li, Liqun Zhang, Pengyan Wen, Shuming Zhang, Jianping Liu, Hui Yang. Effect of microstructure of Au80Sn20 solder on the thermal resistance TO56 packaged GaN-based laser diodes[J]. Journal of Semiconductors, 2020, 41(10): 102104. doi: 10.1088/1674-4926/41/10/102104 ****H Lin, D Y Li, L Q Zhang, P Y Wen, S M Zhang, J P Liu, H Yang, Effect of microstructure of Au80Sn20 solder on the thermal resistance TO56 packaged GaN-based laser diodes[J]. J. Semicond., 2020, 41(10): 102104. doi: 10.1088/1674-4926/41/10/102104.
      Citation:
      Gang Chen, Bo Gao, Min Gong. A dual redundancy radiation-hardened flip-flop based on a C-element in a 65 nm process[J]. Journal of Semiconductors, 2013, 34(9): 095012. doi: 10.1088/1674-4926/34/9/095012 ****
      G Chen, B Gao, M Gong. A dual redundancy radiation-hardened flip-flop based on a C-element in a 65 nm process[J]. J. Semicond., 2013, 34(9): 095012. doi: 10.1088/1674-4926/34/9/095012.
      shu

      A dual redundancy radiation-hardened flip-flop based on a C-element in a 65 nm process

      DOI: 10.1088/1674-4926/34/9/095012
      • 1.

        School of Physical Science and Technology, Sichuan University, Chengdu 610064, China

      • 2.

        Microelectronics Technology Key Laboratory of Sichuan Province, Chengdu 610064, China

      More Information
      • Corresponding author: Gong Min, Email:mgong@scu.edu.cn
      • Received Date: 2013-01-16
      • Revised Date: 2013-03-25
      • Published Date: 2013-09-01

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