1. Introduction

To meet the increasing demands for large volume density SRAM in CMOS technology, two approaches can be taken at device level. The first approach is to scale down the device's dimensions^[1], which has proved effective, but comes at a high cost and became difficult for the deca-nanometer scaled CMOS process^{[2, 3]}. Another approach is to implement an alternative functional device in the cell, so as to obtain a less complex cell structure with smaller SRAM area. In this work, a simple two-terminal vertical memory cell is proposed, which provides excellent potential for high-density integration. Moreover, the new memory cell has only two terminals, such that the cross-point array^[4] with the proposed memory cell becomes conceivable. The cross-point design can achieve the highest integration density in planar technology to date and has great potential for 3-D integration^[5].

2. New memory cell concept

The new memory cell has a vertical four-layer alternatively doped structure with only two terminals, as shown in Fig. 1(a). It exhibits the hysteresis curve shown in Fig. 1(b)^[6]. When the voltage between terminals A and C ($V_{\rm AC})$ increases in the forward direction, the memory cell stays at a low conductance branch until $V_{\rm AC}$ reaches the latch up voltage ($V_{\rm LU})$. At $V_{\rm LU}$, the latch-up^[6] is triggered and the current flowing through the diode ($I_{\rm A})$ increases abruptly. As $V_{\rm AC}$ increases beyond $V_{\rm LU}$, the memory cell gets into a high conductance state and is latched until $V_{\rm AC}$ returns to the latch down voltage ($V_{\rm LD})$ as $V_{\rm AC}$ decreases in the reverse direction, resulting in a bistable region between the latchup and latchdown voltages ($V_{\rm LD}$ < $V_{\rm AC}$ < $V_{\rm LU})$. The memorization mechanism is as following. When $V_{\rm AC}$ is applied between $V_{\rm LD}$ and $V_{\rm LU}$, there are two stable states for the leakage current that can be defined as “1” or “0” ($I_{1}$ or $I_{0}$ respectively). “1” or “0” can be stably conserved once $V_{\rm AC}$ keeps constant. To change the cell into “1” state from “0” state, i.e. to write “1” state, a positive voltage pulse is used to latch up the diode. To change the cell into “0” state from “1” state, i.e. to write “0” state, a negative voltage pulse is used to latch down the PNPN diode. For reading the stored state, the large $I_{1}$/$I_{0}$ ratio ($\approx$10$^{4}$, which will be shown in a later experiment) can be utilized for read operation.

3. Cell design and discussion

This section is divided into four parts: write-1 optimization, write-0 optimization, read operation and discussion. Write-1 optimization discusses the optimization methods used to increase the write-1 speed. Write-0 optimization discusses the optimization method used to increase write-0 speed. The read operation paragraph discusses the read method and the read speed. Finally, the discussion paragraph describes the process variation, reliability, and power dissipation in the retention and writing “1”/“0” operations.

3.1 Write-1 optimization

To begin the study, the PNPN diode, named Cell 1, was fabricated on the CMOS line. Only a few steps were needed, as shown in Fig. 2. The fabrication flow is compatible with the traditional CMOS process and there is no high-temperature process when integrated with the CMOS technology. The doping concentration DP1 and DN2 are at 10$^{20}$ cm$^{-3}$ level, and the N1 and P1 layer are separately at 1 $\times$ 10$^{17}$ cm$^{-3}$ and 1 $\times$ 10$^{18}$ cm$^{-3}$ doping level with the thickness of 0.8 $\mu$m and 0.2 $\mu$m, respectively. For the convenience of direct probe testing, the cell was fabricated with a 50 $\times$ 50 $\mu$m$^{2}$ active cell area, as shown in Fig. 3. Although it has a large area, the fabricated cell can reflect the electronic performances of a small device well due to its quasi 1-D structure (the effect of the diode sidewall surface can be ignored). The measured static $I$–$V$ curve of Cell 1 is given in Fig. 3, which exhibits a good hysteresis property with a high/low conductance current ratio of about 10$^{4}$ times.

Write-1 measurements of Cell 1 were thus made. The measuring circuit is shown in Fig. 4(a). It is hard to measure $I_{\rm A}$ directly, so a resistor was connected in series with the diode and the voltage $V_{\rm A}$ was measured to see the state transition. The first attempt was at hundreds of $\mu$s speed level with a $V_{\rm H}$ $=$ 4.4 V $>$ $V_{\rm LU}$ ($V_{\rm hold}$ is chosen to be 0.8 V and the reason why will be discussed later). The measurement result is shown in Fig. 4(a). We can see that Cell 1 got into the transition state (the definition of transition state is given in Fig. 1(b)) at first and got into “1” state finally as the pulse was over. The measuring result demonstrates that Cell 1 is functional feasible, based on this measure, the measuring speed was increased to hundreds of ns level, which is the limit of our equipment. At this measuring level, we can see that an obvious delay time ($T_{\rm dr})$^[7] exists before Cell 1 gets into the transition state (the blue line in Fig. 4(b)). $T_{\rm dr}$ is the time needed to build up the base regions' charge distribution of the transition state. $T_{\rm dr}$ limits the speed increase of write-1 operation. To increase the write-1 speed, $T_{\rm dr}$ must be reduced. We tried increasing $V_{\rm H}$ to reduce $T_{\rm dr}$. The measuring result is shown Fig. 4(b), we can see that although $T_{\rm dr}$ was reduced to about 50 ns, this delay is still large for ns range operation, moreover, a $V_{\rm H}$ of 4.6 V is high for VLSI and may cause reliability problems.

Besides $V_{\rm H}$, the delay time is also determined by $V_{\rm LU}$. Lower $V_{\rm LU}$ can provide a faster switch-on speed. So we further tried decreasing $V_{\rm LU}$ to reduce $T_{\rm dr}$. $V_{\rm LU}$ can be reduced by decreasing the centre two layers' doping concentrations or increasing the outer two layers' doping concentrations^[6]. In this work, the DP2 was reduced and Cell 2 was obtained with a $V_{\rm LU}$ of 0.95 V, as shown in Fig. 5(a). Pulsed transient measure was thus conducted. In Fig. 5(b), $T_{\rm dr}$ was not observed because it is too small, which indicates that the optimized cell has good potential for high-speed write-1 operation. To study its ns-level performance, a calibrated simulation was used. The fabricated memory cell was first rebuilt with Sentaurus Process simulation^[8]. Then, the Sentaurus Device simulation tool^[8] was used for this rebuilt cell to mimic the measure. The physical models used in device simulations were Fermi statistics; basic mobility model describing the phonon scattering; Masetti model describing the doping dependence of mobility; Canali model describing mobility saturation at high electric field; Slotboom model describing the bandgap narrowing; doping dependent SRH recombination with field enhancement; Auger recombination; surface recombination; nonlocal tunneling; and avalanche multiplication^[9]. The simulation result is given in Fig. 6(a), which shows that a $T_{\rm dr}$ of about 0.6 ns was obtained with a $V_{\rm H}$ of 2.5 V. The simulation indicated that reducing $V_{\rm LU}$ is an effective method to decease $T_{\rm dr}$ and Cell 2 is available for ns level write-1 operation. Moreover, the $T_{\rm dr}$–$V_{\rm H}$ relationship was simulated and is given in Fig. 6(b). It can be seen that Cell 2 has the same $T_{\rm dr}$–$V_{\rm H}$ trend as Cell 1. Based on this relationship, optimization can be used between $T_{\rm dr}$ and $V_{\rm H}$ for practical application.

From Fig. 6(a), it can be seen that there are other two pieces of time that also limit write-1. They are $T_{\rm s}$ and $T_{\rm df}$. In next two paragraphs, we will discuss $T_{\rm s}$ and $T_{\rm df}$ and their optimization method respectively.

$T_{\rm s}$ is important for array operation, it is the time needed to buffer the $T_{\rm dr}$ fluctuation caused by process induced $V_{\rm LU}$ variation. To determine the value of $T_{\rm s}$, the distribution of $V_{\rm LU}$ on the same wafer is measured, as shown in Fig. 7(a). According to the simulated $T_{\rm dr}$–$V_{\rm LU}$ relationship in Fig. 7(b), it can be concluded that the $T_{\rm dr}$ fluctuates between 0.55–0.80 ns. To ensure that all the cells are written into “1” with the same 2.5 V pulse, we only need to ensure the cell with the largest $T_{\rm dr}$ has enough time to be latched-up. Therefore, $T_{\rm s}$ is $0.8-0.6$ $=$ 0.2 ns. $T_{\rm s}$ can be reduced by decreasing the $T_{\rm dr}$ fluctuating range, which can be realized by improving process accuracy. Note that Cell 2 was fabricated on our experimental line and thus process variations could be better controlled in industry.

$T_{\rm df}$ is the time needed to move out the excess charges for the “1” state (the base-region charge amount of the transition state is larger than the “1” states, when the cell starts form the transition state to “1” state, these excess charges needed to be moved out). To increase write-1 speed, $T_{\rm df}$ should be reduced too. $T_{\rm df}$ is determined by $V_{\rm hold}$. The base-region charge amount of the “1” state is directly proportional to $V_{\rm hold}$, which means that more charges need to be moved out when $V_{\rm hold}$ is lower. To demonstrate this point, Cell 2 was simulated with different $V_{\rm hold}$. The simulation results are directly given in Fig. 8(a) and summarized in Fig. 8(b), which demonstrates the $T_{\rm df}$–$V_{\rm hold}$ trend well. Increasing $V_{\rm hold}$ can reduce $T_{\rm df}$ and also increases $I_{1}$ at the same time. Larger $I_{1}$ causes a higher 1-retention power, which will be discussed in later section. Furthermore, as $V_{\rm hold}$ approaches $V_{\rm LU}$, a storage stability problem also occurs. Therefore, comprehensive design is needed when deciding $V_{\rm hold}$. After discussing $T_{\rm dr}$, $T_{\rm s}$ and $T_{\rm df}$ separately, we can clearly see that the necessary time for a successful write-1 operation is the sum of these three pieces of time. For Cell 2, this time is about 1.4 ns, which is available as a SRAM memory cell.

3.2 Write-0 optimization

The write-0 speed is as important as the write-1 speed for a memory cell. To study Cell 2's write-0 speed, negative pulsed transient measures were conducted. From Fig. 9(a), it can be seen that the memory cell was not written into “0” state even when the voltage pulse was increased to $-4$ V towards the negative direction. The reason is that when the memory cell is in “1” state, the base regions are full of excess charges that need a long time ($\mu$s level) to be moved out. To solve this problem, we can reduce the base regions' thicknesses to introduce a punch-through design (PTD)^[9]. The PTD is that the entire base regions are depleted at the designed write-0 voltage, as shown in Fig. 9(b). The PTD can improve the turn-off time by about three orders of magnitude over a traditional PNPN diode. With the PTD, the PNPN diode can be turned off in nanoseconds simply by using the anode to a negative voltage exceeding a certain threshold ($V_{\rm th})$. Based on Cell 2, the N1 layer and P2 layer were reduced to 50 nm and 150 nm respectively in fabrication to introduce the PTD. The newly optimized cell was named as Cell 3. The measured $I$–$V$ curve of Cell 3 is given in Fig. 9(b), from which we can see that a good hysteresis property was kept after the introduction of the PTD. Then, a pulsed transient measure was conducted upon Cell 3, as shown in Fig. 10(a). It can be seen that the write-0 speed was obviously improved; the punch-through threshold voltage $V_{\rm th}$ is about –1.8 V. Once again, simulation was used to study Cell 3's ns-level performance. The simulation result is given in Fig. 10(b), which demonstrates that Cell 3 has an ns-level write-0 speed with available operating voltage for SRAM application. Actually, the write-0 voltage can be further reduced by decreasing base-region thicknesses. The decrease of $V_{\rm L}$ also causes the decrease of storing-0 stability. Therefore, optimization is needed between $V_{\rm L}$ and storing-0 stability. To study whether Cell 3 kept the high-speed write-1 property, the alternative write operations were simulated, as shown in Fig. 11. The simulation demonstrated Cell 3 can be used as a bistable memory cell with steady high-speed programming ability. Table 1 lists the studied cells in the optimization patch.

3.3 Read operation

A current current-latch-based sense amplifier (CLSA)^[10] can be used for read operation. In read operation, the $V_{\rm AC}$ is kept at $V_{\rm hold}$, a CLSA can mirror the current flowing through the memory cell $I_{1}$/$I_{0}$ and output $V_{\rm DD}$/0 V to drive the circuit of next level. The read speed is determined by $I_{1}$, which is about 2 $\times$ 10$^{-5}$ A/$\mu$m$^{2}$. This current level is available for ns level read operation with a nano-level CMOS process.

3.4 Discussion

Besides operation speed, the process variation, reliability and power dissipation (PD) are also important for a memory cell's practical application. The process variation of Cell 3 was measured, which can be directly reflected by the $V_{\rm LU}$ and $V_{\rm LD}$ distributions, as shown in Fig. 12(a). As a simple vertical structure, the process variation can be well controlled. Measures about reliability were also conducted. The $V_{\rm LU}$ and $V_{\rm LD}$ variation with the 3 V to $-3$ V to 3 V sweep (10$^{-8}$ s period) times is given in Fig. 12(b), which indicates the high reliability of the proposed memory cell. At last, the power dissipated in the operations of the proposed cell was studied. To compare with the 45 nm 6T SRAM cell, it was supposed that Cell 3 has a 45 $\times$ 45 nm$^2$ active cell area, which can be realized by using state-of-the-art lithography technology^[11]. There are three kinds of PD in single cell operations. They are retention PD, write PD and read PD. The retention PD is the product of the retention leakage current ($I_{1}$ or $I_{0}$ that depends on the stored state) and $V_{\rm hold}$. Therefore, the 1-retention PD is 40 nW and the 0-retention PD is 100 pW. There are two conditions of write PD: write-1 PD and write-0 PD. Write-1 PD is mainly dissipated in $T_{\rm s}$. Therefore, the average PD in the write-1 cycle is approximately ($V_{\rm H}I_{\rm H})$($T_{\rm S}/T_{1})$ ($T_{1}$ is the write-1 period, $I_{\rm H}$ definition is shown in Fig. 1(b)), which is about 400 nW when $T_{1}$ $=$ 2 ns. For write-0 operation, the PD can be obtained by the integration of ($V_{\rm AC}I_{\rm AC})$/$T_{0}$ ($T_{0}$ is the write-0 period), which is about 100 nW when $T_{0}$ $=$ 2 ns. For read operation, the PD is different in read-1 and read-0 operation. The retention current is used for read, so the read-1 PD and read-0 PD is at the same value with the 1-retention and 0-retention PD separately.

4. Conclusion

Table 2 summarizes the main performance indicators of the proposed memory cell (Cell 3) and the 6T SRAM cell in 45 nm process^{[12, 13]} (in fact, the 6T SRAM cell performance spreads over a wide range depending on the practical application, the data given in Table 2 is a typical range). We can see that the proposed cell offers excellent packing density, low power dissipations with available speed. Moreover, the proposed memory cell is compatible with traditional CMOS technology, has good design flexibility and good reliability due to its gateless structure. It has a great potential in a broad range of applications including embedded memory and stand-alone memory.