J. Semicond. > 2014, Volume 35 > Issue 1 > 015010
|

SEMICONDUCTOR INTEGRATED CIRCUITS

A 130 nm radiation hardened flip-flop with an annular gate and a C-element

Lei Wang, Jianhua Jiang, Yiming Xiang and Yumei Zhou

+ Author Affiliations

 Corresponding author: Wang Lei, Email:wanglei3@ime.ac.cn

DOI: 10.1088/1674-4926/35/1/015010

PDF

Abstract: This paper presents a radiation hardened flip-flop with an annular gate and a Muller C-element. The proposed cell has multiple working modes which can be used in different situations. Each part of the cell can be verified easily and completely by using different modes. This cell has been designed under an SMIC 0.13 μm process and 3-D simulated by using Synopsys TCAD. Heavy-ion testing has been done on the cell and its counterparts. The test results demonstrate that the presented cell reduces the cell's saturation cross section by approximately two orders of magnitude with little penalty on performance.

Key words: SEU, flip-flop, annular gate, C-element



[1]
Petersen E. Single event effects in aerospace. Wiley-IEEE Press, 2010 http://www.wiley.com/WileyCDA/WileyTitle/productCd-1118084314.html
[2]
Nicolaidis M. Design for soft error mitigation. IEEE Trans Device Mater Reliab, 2005, 5(3):405 doi: 10.1109/TDMR.2005.855790
[3]
Gan Xuewen, Wang Xushe, Zhang Xing. Analysis of threshold voltage decreasing for double-gate and surrounding-gate MOSFET's. Chinese Journal of Semiconductors, 2001, 22(12):1581 http://www.oalib.com/paper/1520674
[4]
Mitra S, Seifert N, Zhang M, et al. Robust system design with built-in soft-error resilience. Computer, 2005, 38(2):43 doi: 10.1109/MC.2005.70
[5]
Mitra S, Zhang M, Seifert N, et al. Built-in soft error resilience for robust system design. IEEE International Conference on Integrated Circuit Design and Technology, 2007 http://web.stanford.edu/class/ee386/
[6]
Uemura T, Tosaka Y, Matsuyama H, et al. Robust flip-flop circuit against soft errors for combinational and sequential logic circuits. Jpn J Appl Phys, 2009, 48:04C070 http://adsabs.harvard.edu/abs/2009JaJAP..48dC070U
[7]
Mitra S. Robust system design. 23rd International Conference on VLSI Design, 2010:434
Fig. 1.  Annular gate transistor.

DownLoad: Full-Size Img PowerPoint
Fig. 2.  C-element and its keeper.

DownLoad: Full-Size Img PowerPoint
Fig. 3.  Schematic of the proposed flip–flop.

DownLoad: Full-Size Img PowerPoint
Fig. 4.  3-D modeled transistor.

DownLoad: Full-Size Img PowerPoint
Fig. 5.  The EVD of the different transistors.

DownLoad: Full-Size Img PowerPoint
Fig. 6.  Layout implementation of the proposed flip–flop.

DownLoad: Full-Size Img PowerPoint
Fig. 7.  The chips using an annular gate library.

DownLoad: Full-Size Img PowerPoint
Fig. 8.  The chips using a direct gate library.

DownLoad: Full-Size Img PowerPoint
Fig. 9.  The chips using an annular gate library.

DownLoad: Full-Size Img PowerPoint

Table 1.   Truth table of C-element.

Table 2.   Flip–flop mode list.

Table 3.   Charges generated from SEE pulses.
[1]
Petersen E. Single event effects in aerospace. Wiley-IEEE Press, 2010 http://www.wiley.com/WileyCDA/WileyTitle/productCd-1118084314.html
[2]
Nicolaidis M. Design for soft error mitigation. IEEE Trans Device Mater Reliab, 2005, 5(3):405 doi: 10.1109/TDMR.2005.855790
[3]
Gan Xuewen, Wang Xushe, Zhang Xing. Analysis of threshold voltage decreasing for double-gate and surrounding-gate MOSFET's. Chinese Journal of Semiconductors, 2001, 22(12):1581 http://www.oalib.com/paper/1520674
[4]
Mitra S, Seifert N, Zhang M, et al. Robust system design with built-in soft-error resilience. Computer, 2005, 38(2):43 doi: 10.1109/MC.2005.70
[5]
Mitra S, Zhang M, Seifert N, et al. Built-in soft error resilience for robust system design. IEEE International Conference on Integrated Circuit Design and Technology, 2007 http://web.stanford.edu/class/ee386/
[6]
Uemura T, Tosaka Y, Matsuyama H, et al. Robust flip-flop circuit against soft errors for combinational and sequential logic circuits. Jpn J Appl Phys, 2009, 48:04C070 http://adsabs.harvard.edu/abs/2009JaJAP..48dC070U
[7]
Mitra S. Robust system design. 23rd International Conference on VLSI Design, 2010:434

    • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 2538 Times PDF downloads: 24 Times Cited by: 0 Times

    History

    Received: 23 May 2013 Revised: 14 July 2013 Online: Published: 01 January 2014

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Send
      Article Navigation >  Journal of Semiconductors  > 2014  >  35(1): 015010
      Lei Wang, Jianhua Jiang, Yiming Xiang, Yumei Zhou. A 130 nm radiation hardened flip-flop with an annular gate and a C-element[J]. Journal of Semiconductors, 2014, 35(1): 015010. doi: 10.1088/1674-4926/35/1/015010 ****L Wang, J H Jiang, Y M Xiang, Y M Zhou. A 130 nm radiation hardened flip-flop with an annular gate and a C-element[J]. J. Semicond., 2014, 35(1): 015010. doi: 10.1088/1674-4926/35/1/015010.
      Citation:
      Lei Wang, Jianhua Jiang, Yiming Xiang, Yumei Zhou. A 130 nm radiation hardened flip-flop with an annular gate and a C-element[J]. Journal of Semiconductors, 2014, 35(1): 015010. doi: 10.1088/1674-4926/35/1/015010 ****
      L Wang, J H Jiang, Y M Xiang, Y M Zhou. A 130 nm radiation hardened flip-flop with an annular gate and a C-element[J]. J. Semicond., 2014, 35(1): 015010. doi: 10.1088/1674-4926/35/1/015010.
      shu

      A 130 nm radiation hardened flip-flop with an annular gate and a C-element

      DOI: 10.1088/1674-4926/35/1/015010

      • Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

      More Information
      • Corresponding author: Wang Lei, Email:wanglei3@ime.ac.cn
      • Received Date: 2013-05-23
      • Revised Date: 2013-07-14
      • Published Date: 2014-01-01

      Catalog

        Journal of Semiconductors © 2017 All Rights Reserved   京ICP备05085259号-2

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return