1. Introduction

All digital phase-locked loops (ADPLLs) are widely used in the on-chip clock generators. The common architecture of a DCO consists of a digitally controlled oscillator, a frequency divider, a phase frequency detector and a controller, as shown in Fig. 1^[1]. The definition and operation of functional blocks have become very convenient nowadays due to digital circuit implementation. Delay, area and power consumption have kept on reducing while the process technology is scaling down. The performance of ADPLLs is improved a great deal under deep submicron technology and nanometer technology^[2].

The DCO is the most important component of ADPLL and dominates the performance of ADPLL. The function of the DCO is to generate a clock signal whose frequency is proportional to the digital control code. A DCO is very similar to a voltage controlled oscillator except that the DCO's frequency is tuned digitally while the VCO's frequency is tuned by an analog signal^[3]. As the scaling down of the process technology, a higher frequency can be generated after using fine-tuning delay cells. But in real applications, DCO delay may not meet the specified target with a large frequency range when working on the mid-low frequency or wideband frequency. An easy way to increase the coverage is by adding delay cells, but this will increase the area and leakage current significantly. Another way to achieve this, which can save the area, is dividing the high frequency signals. But the adjustable resolution is very limited with this method. So the multi-stage coarse-fine DCO architecture is commonly used to meet the frequency range and resolution requirements^[4-9].

The coarse-fine DCO architecture can use large coarse delay units to increase the period range effectively. Cascaded hysteresis delay cells (CHDC)^[8] are proposed for large delay generation with a relatively low power consumption and small area. Compared with traditional methods using buffers^{[4, 6]} and logic gates^{[5, 7, 9]}, the power consumption and area are greatly reduced. However, some internal nodes in this design are weakly driven, and the process, voltage and temperature (PVT) variations of the CHDC delay cell are high. In order to guarantee a continuous period change, the fine-tuning stage should cover a wider range, so that more power and area will be consumed. Interlaced hysteresis delay cells (IHDC)^[10] are proposed to get very large delays while the power is low and the area is small. The delay is generated through the signals interleaving changed between the two series of transistors. The benefit of this design is to avoid a short current and use a shared path to save leakage current. In addition to this, the internal nodes are all rail to rail so that PVT variations are reduced. However, the power consumption and phase noise of the IHDC still have the potential for optimization.

A DCO using inverters interlaced cascaded as delay cell (IICDC) is proposed in this article to get more timing delays while keeping the very low power consumption and small area. Compared with IHDC^[10], our design also uses interleaving changed signals between two serials of transistors to generate the delay with the benefits of short current prevention, leakage current saving by path sharing, rail-to-rail internals nodes, and small PVT variations. The most important point is that the power consumption is greatly lowered while the phase noise is still low.

2. The DCO structure and the design of IICDC

2.1 DCO structure

The overall architecture of the DCO is shown in Fig. 2^[11]. The coarse-fine architecture is used with two stages of coarse tuning and one stage of fine tuning, which is controlled by an 11 bits period code. A binary-weighted control structure is used for both course tuning and fine tuning, which means the delay of the later stage is half of the previous stage.

The control code of the coarse tuning stage uses a multiplexer to decide whether or not the controlled delay will be applied to the oscillation loop. The delay unit of the second coarse tuning stage is the IICDC, which will generate most of the delay. Compared with the conventional delay cell, the IICDC can provide more timing delay while consuming lower power, a smaller area and generating lower phase noise. The delay cell structure will be discussed in detail in the following section.

The fine-tuning stage is regulated by the digital controlled varactors (DCV) on the delay path. The load of varactors could be selected by the fine-tuning control code to adjust the delay of the path. The method has high resolution and good linearity. The decoder could be eliminated after using the binary-weighted code control structure.

2.2 Design of IICDC

The circuit configuration of IICDC-2 is shown in Fig. 3. The delay of the circuit is achieved by the two series of cascade pMOS and nMOS transistors (M1-M8). The nodes marked by the same characters such as A, B, C are connected together. The connections of these nodes are not drawn in order to keep the diagram clear and clean. The IICDC-2 operation timing diagram is illustrated in Fig. 4. Supposing the initial voltage at node IN is high. After IN goes to low, M1 is turned on and node A is pulled to the high voltage. M8 is turned on due to the high voltage at nodes A and B, which is discharged to low voltage. After this, M2 is turned on and node C is charged into high voltage, which will turn on M7 and force node OUT to be low. In summary, the falling edge of the signal at node IN will propagate through M1, M8, M2 and M7 to node OUT. Similarly, the rising edge at node IN will pass through M5, M3, and M6 to node OUT. From these analyses, the delay path is interlaced between these two series of cascaded transistors. The drain node of M1 is connected to the drain node of M4 through node A to avoid the weakly driven status. Similarly, M5 and M8 are connected through node B to ensure they could be charged or discharged to a stable status. So the voltage swing of all the internal nodes is rail to rail.

As displayed in the IICDC circuit structure, pMOS and nMOS are turned on and off one after another in different paths, so no short current exists. As the delay cells are based on an inverter and the signals take a long time to propagate through, the short current is the main power consumption of this structure. In addition to this, there are only two power related paths between the power supply and the ground. The transistors on the same path have the leakage charge sharing effect to limit the leakage current. So the more transistors cascaded in the same path, the more leakage power could be saved. Due to the perfect symmetry of the interlaced structure, the design with more cascaded transistors could be easily achieved, which is shown in Figs. 5 and 6 about the design of IICDC-3 and IICDC-4.

3. IICDC simulation and analysis

We have made a comparison between the IHDC and our designed IICDC delay cells using 0.18 $\mu$m process technology simulation results. The delay cells are connected into ring oscillators. The number of delay cells is tuned to keep the frequency at 100 MHz. The Cadence Spectre Circuit Simulator is used for the simulation and the errpreset parameter is set to conservative.

3.1 Power comparison of IHDC and IICDC

The architecture of the IHDC delay cell^[10] is shown in Fig. 7 and the measurement of the IHDC unit transient simulation results at nodes a, c, e is displayed in Fig. 8. It is notable of node d in the second stage that a path exists from the power supply to the ground, which happens at around 89 ns. Therefore, the power consumption will be increased due to the short current. To be specific, around 89 ns, node e is low and pMOS is on. Node c is high and nMOS M8 is on. At the same time, node a is high and nMOS M12 is also on. Hence the power supply is connected to the ground through M9, M8 and M12. Current will go through this path within an approximate 0.5 ns and this current does not charge or discharge any related nodes. So this portion of the power is wasted and does not contribute to the delay function of the circuit.

At the same time, from the transient simulation of the IICDC unit, which is shown in Fig. 9, there are two transistors (pMOS and nMOS) on the power supply to the ground path and these two transistors will not be on at the same time. So there is no direct path from the power supply to the ground and all the currents are used for charging and discharging the capacitor of the internal nodes. That is to say, the power efficiency is very high and the overall power consumption is very low.

3.2 Phase noise comparison of IHDC and IICDC

For a ring oscillator, assuming it is a liner system, the overall phase change can be calculated from the superposition principle, which is shown in Eq. (1)^[12].

$\begin{eqnarray*} \phi(t)=\frac{1}{q_{\rm max}}\int^t_{-\infty}i(\tau)\left[\sum^{N-1}_{n=0}\mathit{\Gamma }\left(\omega_0\tau+\frac{2\pi n}{N} \right) \right]{\rm d}\tau. \end{eqnarray*}$

(1)

In the equation, $q_{\rm max}$ is the maximum charge change of the capacitor. $\mathit{\Gamma }$ is the impact sensitivity function (ISF). $i(\tau)$ is the total noise current injection.

Regarding $\mathit{\Gamma } \left(\omega_0\tau+\frac{2\pi n}{N} \right)$, it could be approximated by a triangle^[13], which is shown in Fig. 10. The root mean square of $\mathit{\Gamma }$ could be calculated by the following Eq. (2).

$\begin{equation} \mathit{\Gamma }^2_{\rm rms}=\frac{1}{3\pi}\left(\frac{1}{f_{\rm rise}} \right)^3(1+A^3). \end{equation}$

(2)

In Eq. (2), $f_{\rm rise}$ and $f_{\rm fall}$ are the maximum slopes of the rising edge and falling edge. $A$ is the ratio of $f_{\rm rise}$ and $f_{\rm fall}$.

From the analysis above, phase change is mainly dependent on the total noise current of the node $i(\tau)$ ISF and stage number $N$ of the ring oscillator. So the phase noise could be reduced from these three aspects.

The analysis of noise current $i(\tau)$ comes first. From the architecture of IICDC, which is illustrated in Figs. 3, 5, and 6 and the architecture of IHDC^[10], the total noise current of the internal nodes is mainly from the noise of the transistors. So the noise is proportional to the number of transistors, assuming the transistors are the same size. Therefore, the noise current of IICDC-4 is approximately 57% of IHDC-LV4.

Second, in regard to ISF, which is shown in Eq. (2), the $f_{\rm rise}$ of the internal nodes in IICDC-4 is one time faster than IHDC-LV4 and the $f_{\rm fall}$ of IICDC is also around 20% faster, which can be seen from Fig. 11. In Eq. (2), $A$ is the ratio of $f_{\rm rise}$ and $f_{\rm fall}$, as $f_{\rm rise}$ is much smaller than $f_{\rm fall}$, so the third power of A is much smaller than 1 and can be ignored in Eq. (2). Therefore, $\mathit{\Gamma }_{\rm rms}^2$ is approximately proportional to $\left(\frac{1}{f_{\rm rise}} \right)^2$. After an easy calculation based on the data in Fig. 11, the $\mathit{\Gamma }_{\rm rms}^2$ of IICDC is only 1/8 of IHDC. Hence ISF is reduced by $\left(\frac{1}{n} \right)^{1/2}$.

Third, when it comes the stage number $N$ of the ring oscillator, since the delay of IICDC is smaller than IHDC, the number $N$ of IICDC-4 will be almost doubled in simulation compared to IHDC-LV4.

From the discussion of these three aspects above, it can be calculated from Eq. (1) that $\phi(t)$ of IICDC-4 is around one fifth of IHDC-LV4.

3.3 Simulation results

According to the simulation results in Table 1, it confirms the conclusion of our theoretical analyses. IICDC has better performance on power consumption, although the area is increased slightly. In regard to the phase noise, there is deviation between the simulation results and theoretical analyses above due to the approximate calculation and some ignored factors. It still shows that the phase noise is greatly improved in IICDC.

4. Experiment results

The ADPLL is implemented using the architecture in Fig. 1 and fabricated by UMC 0.18 $\mu$m RF 1P6M technology. DCO is designed with the architecture in Fig. 2. Figure 13 is the snapshot of the chip. The total area of the ADPLL chip is 0.071 mm$^{2}$ and the area of the DCO is 0.0051 mm$^{2}$. The core power supple voltage is 1.8 V. When the ADPLL is working at 200 MHz, the power consumption is 2.34 mW based on the current measurement and the RMS period jitter is 42 ps measured by the Agilent oscilloscope, which is shown in Fig. 12. The output frequency of the ADPLL is from 140 to 600 MHz. A comparison among several designs is shown in Table 2. The measurement results of the delay range and step resolution are listed in Table 3.

From the data in Table 2, our design consumes more power and area than Ref.[10] because of the process technology difference and the complex design of the control loop.

From the discussion in Section 3, IICDC consumes less power than IHDC while getting the same timing delay. In addition to this, the phase noise of IICDC is also better than IHDC. From the data in Table 2, our ADPLL design using the IICDC structure has better RMS period jitter than IHDC. However, the area and power are higher than IHDC due to the following reasons:

(1) The process technology is different. Area usage and power consumption will benefit from smaller process technology. (2) The other blocks in our ADPLL design are very complex and consume more power and area. (3) The number of IICDC units used in this design is relatively small. So the advantage of power consumption could not be shown well. (4) In spite of the impact of the layout design, parasitic effect and other non-ideal factors, the RMS period jitter of IICDC is still improved.

5. Conclusion

This paper introduces a novel design of an inverter interlaced cascaded delay cell (IICDC) with low power, low phase noise and small area. The low power and low phase noise benefits are also analyzed in detail. The ADPLL using the IICDC cells is designed and fabricated by UMC 0.18 $\mu$m process technology. The measurement results show that the full chip power consumption is 2.34 mW at 200 MHz and the RMS period jitter is 42 ps. The results illustrate that using the IICDC design as delay cells can largely improve the power consumption and phase noise under low frequency and a wide period range.