1. Introduction

High-speed dividers are widely used in optical fiber communication systems, wireless communication systems, test systems and so on. With the development of the CMOS process, the design of the high-speed frequency divider based on the CMOS process has great practical significance undoubtedly. A classic 2$^{n}$/2$^{n}$+1 dual-modulus divider is composed of a synchronous divider and an asynchronous divider, which has the advantages of simple structure, powerful stability, and nimble expansibility due to the fact that the division ratio can be changed easily by increasing or decreasing the series of 2 asynchronous divider^{[1, 2]}. But because of the synchronous divider section working at the highest frequency, sometimes power dissipation is larger. In this paper an improved 2$^{n}$/2$^{n}$+1 dual-modulus divider structure is proposed, which can make all separated logic gates embed into correlative D flip-flops completely so as to get a fully integrated frequency divider. In this way, the amount of components can be reduced effectively and the circuit can avoid the influence of parasitic parameters caused by the separated logic gate, therefore excellent performances of higher speed and lower power dissipation are achieved. In addition, a low-voltage bandgap reference is designed to generate an adjustable reference voltage with zero temperature coefficient for the above frequency divider.

2. High-speed dual-modulus divider design

The traditional circuit of 8/9 divider is shown in Fig. 1, which is composed of 4/5 synchronous divider and 2 asynchronous divider. The circuit works at divide-by-8 when MC = 0, and divide-by-9 when MC = 1.

Notice that the logic gates L1, L2, L3 are located in the critical path. If they can be incorporated into correlative D flip-flops, the power consumption will decrease and the circuit will operate more effectively. Applying De Morgan's Theorem, the following expressions can be obtained.

$$\begin{equation} {\rm D1}={\rm Q}_2^{ n} +\overline {{\rm MC}\cdot \overline {{\rm Q}_4^{ n} } } ={\rm Q}_2^{ n} +\overline {\rm MC} +{\rm Q}_4^{ n} . \end{equation}$$

(1)

That is, L1 and L2 can be combined to only one 3-input OR gate L as shown in Fig. 2, except that the circuit is controlled by the inverted MC.

So the improved circuit will work at divide-by-8 when MC = 1, and divide-by-9 when MC = 0 shown in Fig. 3. Compared with Figs. 3 and 1, the improved structure is further simplified, and all separated logic gates are incorporated into correlative D flip-flops completely. In this way, the complex logic functions can be performed with a minimum number of devices and with maximum speed, so that lower power consumption and higher speed are obtained.

F2, F4 in Fig. 3 can be designed using SCL topology to be edge-triggered and differentially clocked^{[3, 4]}. The cascade structure of two basic high-speed D-latches is shown in Fig. 4. The master latch (the left one) will assume the state determined by the D2 (D4) and $\overline {\rm D} 2$ $(\overline {\rm D} 4)$ inputs when CLK = 1, $\overline{\rm CLK}$ = 0 which is then transferred to the slave latch (the right one) when CLK = 0, $\overline{\rm CLK}$ = 1. At the falling edge of the clock pulse, the state of the slave latch then appears on the Q2 (Q4) and $\overline {\rm Q} 2$ ($\overline {\rm Q} 4)$ outputs.

Figure 5 shows the circuit structure of D flip-flop F1 integrated with 3-input OR gate. The two additional transistors MA1' and MA1'' are connected with MA1 in parallel, while the former transistor MA2 is connected to the reference voltage $V_{\rm REF}$ provided on chip. If all inputs are LOW, MA1, MA1' and MA1'' cut off, while MA2 is biased on its active region. If any input is HIGH, the corresponding input transistor turns on and MA2 turns off. This means that the OR/NOR logics are obtained at outputs.

Figure 5 indicates that integrating logic functions into a circuit rather than using separated logic gates will reduce the number of devices required remarkably, as well as the propagation delay time. The above-mentioned principle also applies to F3 if removing one input transistor MA1".

3. Low-voltage bandgap reference design

Another circuit is required to provide the reference voltage $V_{\rm REF}$^{[5, 6]}. The adjustable low-voltage bandgap reference on chip is shown in Fig. 6. Transistor T2 consists of $n$ unit transistors in parallel, and T1 is a unit transistor. Each transistor is biased by a PMOS current source to ensure that the bias currents of both transistors have the same behavior with temperature^{[7, 8]}.

If M2, M3 are identical to M1, and the OPA ensures that $V_{\rm X}=V_{\rm Y}$, thus

$$\begin{equation} \begin{split} V_{\rm REF} {}& =R_3 I_3 =R_3 I_2 \\[1mm]& =R_3 (I_{\rm R4} +I_{\rm R2} ) \\[1mm]& =R_3 \left(\frac{V_{\rm EB1} }{R_4 }+\frac{V_{\rm EB1} -V_{\rm EB2} }{R_2 }\right) \\[1mm]& =\frac{R_3 }{R_4 }V_{\rm EB1} +\frac{R_3 }{R_2 }V_{\rm T} \ln n, \\ \end{split} \end{equation}$$

(2)

the parameter $V_{\rm T}$ is approximately $V_{\rm T}$ = 26 mV at room temperature, $T=$ 300 K.

Making $\frac{\partial V_{\rm REF} }{\partial T}=0$, then

$$\frac{R_3 }{R_4 }\frac{\partial V_{\rm EB1} }{\partial T}+\frac{R_3 }{R_2 }\ln n\frac{\partial V_{\rm T} }{\partial T}=0,$$

and hence

$$\frac{R_3 }{R_2 }\ln n=-\frac{R_3 }{R_4 }\frac{\partial V_{\rm EB1} }{\partial {\rm T}}/\frac{\partial V_{\rm T} }{\partial T}.$$

Since at room temperature, $\frac{\partial V_{\rm EB} }{\partial T}\approx -1.5$ mV/$^\circ$K, $\frac{\partial V_{\rm T} }{\partial T}\approx$ 0.087 mV/$^\circ$K^[9], such that

$$\begin{equation} \frac{R_3 }{R_2 }\ln n\approx \frac{R_3 }{R_4 }\times 17.2. \end{equation}$$

(3)

Substituting Eq. (3) into Eq. (2), the following expressions for $V_{\rm REF}$ can be obtained:

$$\begin{equation} \begin{split} V_{\rm REF} {}& \approx \frac{R_3 }{R_4 }V_{\rm EB1} +V_{\rm T} \frac{R_3 }{R_4 }\times 17.2 \\& \approx \frac{R_3 }{R_4 }(V_{\rm EB1} +17.2V_{\rm T} ) \\& \approx \frac{R_3 }{R_4 }\times 1.25\;{\rm V}. \\ \end{split} \end{equation}$$

(4)

Suggesting that, an adjustable output voltage with zero temperature coefficient at room temperature can be realized by paralleling the minimum number of resistors next to the bipolar transistor (BJT).

4. Simulation and measured results

The high-speed dual-modulus divider is fabricated in 0.18~$\mu $m standard CMOS process. Its microphotograph is shown in Fig. 7.

The measured results show that, in the frequency range of 1.1-2.5 GHz, the circuit can work normally. The 8/9 divider consumes 1.1 mA in 1.8 V power supply. The measured output frequency spectrum at divide-by-8 mode and the tested output waveform at divide-by-9 mode with 1.5 GHz input signal are given in Figs. 8 and 9, respectively. Operating at a 1.8 V supply, the adjustable bandgap reference can produce a 1.0 V output and its power supply rejection ratio (PSRR) can reach around $-48$ dB at low frequency. The simulated voltage drift with temperature is shown in Fig. 10, which demonstrates that its temperature coefficient (TC) will equal to 8.3 ppm/℃.

5. Conclusion

In this paper an improved fully integrated, high-speed, dual-modulus divider based on high-speed D flip-flop is designed in 0.18 $\mu $m standard CMOS process, and an adjustable low-voltage bandgap reference needed by the frequency divider is obtained. The performances are compared with other previous work as shown in Table 1. By comparison, the design of the dual-modulus divider in this paper possesses better performance and flexibility.