1. Introduction

At present, a bandgap reference circuit has been used as a basic block in integrated circuits^[1-7]. The reference will directly affect the accuracy of the whole circuit system. Therefore, the study of various error sources that exist in the reference and compensation of this error is particularly important. Here, according to the ideas of Gupta and Rincón-Mora who have studied them, is the given trimming scheme^[8].

In the bandgap reference, there are many factors that will give rise to precision errors, such as, base-emitter voltage spread and matching of the transistor, tolerances and resistor^[8]. Unfortunately, these errors are inevitable. In order to solve these error sources and obtain high-precision components, Section 2 will present the analysis and quantitative calculation of each error source. In Section 3, the compact binary-weighted resistor trim schemes were used to compensate the error. The chip prober data is obtained before trimming and after. The conclusion is given in Section 4.

2. Error sources

Figure 1 shows the schematic of a bandgap reference circuit in bipolar technology. The voltage drop across $R_{2}$ and $R_{3}$ is identical because of the amplifier. The resistance of $R_{3}$ is 3 times that of $R_{2}$ and the current flowing in $R_{2}$ is 3 times that of $R_{3}$. The current flowing in $R_{1}$ is the sum of currents. The reference voltage in Fig. 1 is

$\begin{equation} V_{\rm REF} =V_{\rm BE1} +V_{\rm BE2} +I_{\rm C2} R_2 +I_{\rm C1} R_1, \end{equation}$

(1)

where $V_{\rm BE1}$ and $V_{\rm BE2}$ are the base-emitter voltage of transistors Q1 and Q2. $I_{\rm C1}$ and $I_{\rm C2}$ are the current flowing through resistors $R_{1}$ and $R_{2}$. Equation (1) can be written as

$\begin{equation} \begin{split} V_{\rm REF} ={}& V_{\rm T} \ln \frac{I_{\rm C1} }{I_{\rm S1} }+V_{\rm T} \ln \frac{I_{\rm C2} }{I_{\rm S2} }+ \left( {\frac{V_{\rm T}}{R_4 }\frac{R_3 }{R_2 }\ln C} \right)R_2 \\& +\left( {\frac{V_{\rm T} }{R_4 }\frac{R_3 }{R_2 }\ln C+\frac{V_{\rm T}}{R_4 }\ln C} \right)R_1, \end{split} \end{equation}$

(2)

where $C$ is the ratio of the current densities of Q2 and Q3.

By applying the mathematical analysis of error sources to Eq. (2), the derivative of the reference voltage is given as

$\begin{equation} \begin{split} \Delta V_{\rm REF} ={}& \frac{\partial V_{\rm BE1} }{\partial I_{\rm S1} }\Delta I_{\rm S1} +\frac{\partial V_{\rm BE2} }{\partial I_{\rm S2} }\Delta I_{\rm S2} +\frac{\partial V_{\rm BE1} }{\partial I_{\rm C1} }\Delta I_{\rm C1} \\& + \frac{\partial V_{\rm BE2} }{\partial I_{\rm C2} }\Delta I_{\rm C2} +\frac{\partial I_{\rm C2} R_2}{\partial R_4 }\Delta R_4 + \frac{\partial I_{\rm C2} R_2 }{\partial C}\Delta C \\& + \frac{\partial I_{\rm C2} R_2 }{\partial {R_3 }/{R_2 }}\Delta \frac{R_3 }{R_2 } +\frac{\partial I_{\rm C2} R_2 }{\partial {R_2 }/{R_4 }}\Delta \frac{R_2 }{R_4 }+\frac{\partial I_{\rm C2} R_2 }{\partial R_2 }\Delta R_2 \\& + \frac{\partial I_{\rm C1} R_1 }{\partial R_4 }\Delta R_4 +\frac{\partial I_{\rm C1} R_1 }{\partial C}\Delta C+ \frac{\partial I_{\rm C1} R_1 }{\partial {R_1 }/{R_4 }}\Delta \frac{R_1 }{R_4} \\& +\frac{\partial I_{\rm C1} R_1 }{\partial R_1 }\Delta R_1 +\frac{\partial I_{\rm C1} R_1 }{\partial {R_3}/{R_2 }}\Delta \frac{R_3 }{R_2}. \\ \end{split} \end{equation}$

(3)

The magnitude of the error in reference $V_{\rm REF}$ is obtained by comparing the reference voltage of an "ideal" reference, where the particular error sources are process-induced. The magnitude of error $\Delta I_{\rm S}$ is the error of the transfer characteristic of the transistor, $\Delta I_{\rm S}$ $=$ $I_{\rm S}\delta _{\rm S}$ ($\delta _{\rm S}$ is the error ratio of the transistor's transfer characteristic). Furthermore, $\Delta I_{\rm C1}$ and $\Delta I_{\rm C2}$ are the collector current errors of the two bipolar transistors Q1 and Q2, and the derivatives of the collector currents are given as

$\begin{equation} \begin{split} \Delta I_{\rm C1} {}& =\frac{\partial I_{\rm C1} }{\partial R_4 }\Delta R_4 +\frac{\partial I_{\rm C1} }{\partial C}\Delta C+\frac{\partial I_{\rm C1} }{\partial {R_3}/{R_2 }}\Delta \frac{R_3 }{R_2 } \\& \approx -\frac{I_{\rm C1} }{R_4 }\Delta R_4 +\left( {1+\frac{R_3 }{R_2 }} \right)\frac{V_{\rm T}}{R_4 }\frac{1}{C}\Delta C, \end{split} \end{equation}$

(4)

$\begin{equation} \begin{split} \Delta I_{\rm C2} {}& =\frac{\partial I_{\rm C2} }{\partial R_4 }\Delta R_4 +\frac{\partial I_{\rm C2} }{\partial C}\Delta C+ \frac{\partial I_{\rm C2} }{\partial {R_3}/{R_2 }}\Delta \frac{R_3 }{R_2 } \\& \approx -\frac{I_{\rm C2} }{R_4 }\Delta R_4 +\frac{R_3 }{R_2 }\frac{V_{\rm T}}{R_4 }\frac{1}{C}\Delta C, \end{split} \end{equation}$

(5)

where the factors that the errors of resistor $R_{4}$, $C$ and matching resistor $R_{3}/R_{2}$ give rise to $\Delta I_{\rm C1}$ and $\Delta I_{\rm C2}$, then Equations (4) and (5) have described them. The magnitude error of $R_{4}$ is $\Delta R_{4}$ $=$ $R_{4}\delta _{\rm RA}$ ($\delta _{\rm RA}$ is the error ratio of resistor tolerance). The magnitude error of $C$ is $\Delta C=C\delta _{\rm NPN}$ ($\delta _{\rm NPN}$ is the error ratio of the transistor matching^[8]. The matching tolerance of resistors $R_{3}/R_{2}$ is negligible due to their ratio. In layout, identical resistor geometries are used^[9]. Namely, the resistor $R_{3}$ is 3 times that of the resistor $R_{2}$, and this allows ways to be devised to minimize the matching error of the pair of resistors.

The tolerances of resistors $R_{1}$ and $R_{2}$ are $\Delta R_{1}$ $=$ $R_{1}\delta_{\rm RA}$, $\Delta R_{2}$ $=$ $R_{2}\delta _{\rm RA}$. The matching tolerance exists in the pair of resistors. While the matching error of pairs $R_{1}/R_{4}$ and $R_{2}/R_{4}$ is larger than the $R_{3}/R_{2}$ pair of resistors, they are significant. They can be described as $\Delta R_{1}$/$R_{4}$ $=$ $R_{1}/R_{4}$ $\times$ $\delta _{\rm RR}$, $\Delta R_{2}$/$R_{4}$ $=$ $R_{2}/R_{4}$ $\times$ $\delta_{\rm RR}$ ($\delta _{\rm RR}$ is the error ratio of resistor matching tolerance). By substituting Eqs. (4), (5) and other parameter tolerances into Eq. (3), the error of the reference voltage is given by

$\begin{equation} \begin{split} \Delta V_{\rm REF} ={}& -2\Delta V_{\rm BE} -2V_{\rm T} \delta _{\rm RA} +2\frac{V_{\rm T}}{\ln C}\delta _{\rm NPN} + 3\frac{V_{\rm T}}{R_4 }R_2 \delta _{\rm NPN} \\& +4\frac{V_{\rm T}}{R_4 }R_1 \delta _{\rm NPN} +3V_{\rm T} \ln C\frac{R_2 }{R_4 }\delta _{\rm RR} \\& +4V_{\rm T} \ln C\frac{R_1 }{R_4 }\delta _{\rm RR}, \end{split} \end{equation}$

(6)

where -2$\Delta V_{\rm BE}$ is the transistors of the Q1 and Q2 base-emitter voltage spread, 3$V_{\rm T}$ln$C$ $\times$ ($R_{2}/R_{4})$ $\times$ $\delta_{\rm RR}$ $+$ 4$V_{\rm T}$ln$C$ $\times$ ($R_{1}/R_{4})$ $\times$ $\delta _{\rm RR}$ is the resistor matching tolerances, -2$V_{\rm T}$ $\delta _{\rm RA}$ is the resistor tolerances and 2$V_{\rm T}$/ln$C$ $\times$ $\delta _{\rm NPN}$ $+$ 3$V_{\rm T}$($R_{2}/R_{4})$ $\times$ $\delta _{\rm NPN}$ $+$ 4$V_{\rm T}$($R_{1}/R_{4})$ $\times$ $\delta _{\rm NPN}$ is the matching tolerances of the transistors.

2.1 Transistor base-emitter voltage ($\boldsymbol{V_\textbf{BE}}$) spread and analytic values

$V_{\rm BE}$ spread is the considerable error source and is critical because it exists in process biases. A number of factors give rise to this error, such as the width of the base $W_{\rm B}$, the cross-sectional area of the emitter A, the equilibrium concentration of electrons in the base $n_{\rm p0}$, the diffusion capacity for electrons $D_{\rm n}$, and etc^[10]. These parameters are constants according to the ideal state in a general quantitative calculation. In fact, these parameters will deviate from the ideal values. They will be directly reflected in the error of the reference voltage, the value is $\Delta V_{\rm BE}=\pm$24 mV^[11]. By substituting the $\Delta V_{\rm BE}$ values into part of Eq. (6) using $V_{\rm BE}$ spread, the following results can be obtained

$\begin{equation} \Delta V_{\rm REF} =\pm 48\, {\rm mV}. \end{equation}$

(7)

2.2 Transistor matching tolerances

The references use matched bipolar transistors Q2 and Q3 to produce known voltages and currents. This error source comes from matched bipolar transistors Q2 and Q3. NPN collector currents scale approximately with the drawn emitter area, the mismatch of them between a pair of transistors is due to the emitter area fluctuations^[8]. By substituting the $\delta _{\rm NPN}$ value into part of Eq. (6) using the matching tolerances of the transistors, at room temperature, the error in the reference voltage is given by

$\begin{equation} \Delta V_{\rm REF} =2\frac{V_{\rm T}}{\ln C}\delta _{\rm NPN} +3V_{\rm T} \frac{R_2 }{R_4 }\delta _{\rm NPN} +4V_{\rm T} \frac{R_1 }{R_4 }\delta _{\rm NPN} . \end{equation}$

(8)

2.3 Resistor tolerance

During the production of devices, resistor tolerances will trigger a change of the current thereby directly causing a transistor base-emitter voltage change $\Delta V_{\rm BE}$ and the collector current changes $\Delta I_{\rm C}$. The value of $\delta _{\rm RA}$ is 20%^[8]. By substituting the $\delta _{\rm RA}$ values into part of Eq. (6) using resistor tolerances, at room temperature, the following results can be obtained:

$\begin{equation} \Delta V_{\rm REF} =-2V_{\rm T} \delta _{\rm RA} . \end{equation}$

(9)

2.4 Resistor matching tolerances

Resistors with different widths, lengths or shapes can easily experience mismatches of $\pm$1% or more, and they are not neglected. When designing the layout, some matching rules can be applied for each process to obtain matched devices with a desired degree of accuracy. In the quantitative calculation, these resistor matching tolerances will not disappear.

$\delta _{\rm RR}$ is the ratio of resistor matching tolerance. We assume that these contacts have a process bias of 0.2 $\mu$m^[8]. Considering the case of matched resistors having the same widths of 6 $\mu$m, if the matched resistors $R_{1}$, $R_{2}$, $R_{4}$ were 114 $\mu$m, 68.4 $\mu$m, 27 $\mu$m long, respectively, then the mismatch caused by this bias would equal 4.191, 2.522, $\delta _{\rm RR}$ represents an about 2% mismatch of the resistors. Substitution of the $\delta _{\rm RR}$ values into part of Eq. (6) by resistor matching tolerances, at room temperature, the following results can be obtained:

$\begin{equation} \Delta V_{\rm REF} =3V_{\rm T} \ln C\frac{R_2 \delta _{\rm RR} }{R_4 }+4V_{\rm T} \ln C\frac{R_1 \delta _{\rm RR} }{R_4 }. \end{equation}$

(10)

2.5 The sum of tolerances in the reference voltage

The previous sections have described the various error sources responsible for causing the base-emitter voltage spread and matching of the transistor, tolerances and matching of the resistor and transistor. If each parameter value is substituted into Eqs. (7)-(10), the analytic value of every error source will be calculated. At room temperature, the transistors of the Q1 and Q2 base-emitter voltage spread is constant ($\pm$24 mV), the resistor matching tolerance is 13.34 mV, the resistor tolerance is -10 mV and the transistor matching tolerance is 22.85 mV. The total trimming voltage is 111 mV according to the calculated RMSE $\pm$55.71 mV. From Eq. (6), the error of the reference is the linear function to the temperature. It can be described as Fig. 2.

Figure 3 shows the simulation results from the analytical value of reference. At room temperature (Tr), the typical reference is 2.495 V^[12], the fast and slow voltages are 2.508 V and 2.483 V with the 111 mV trimming. The upper and lower extremes of the reference precision are compensated to temperature because the reference is compensated. To the lower extreme of precision, the worst case exists at the limiting temperature and the upper at 60 ℃.

3. Trimming scheme and experiment

In Fig. 4, the binary-weighted series-connected resistor trim schemes can minimize the error sources. The binary-weighted resistor is 312 $\Omega$/156 $\Omega$/78 $\Omega$/39 $\Omega$ with respect to extra voltage 56 mV/28 mV/14 mV/7 mV. However, the actual voltage is 60 mV/30 mV/14 mV/7 mV because of the additional contact resistor. The sum of extra voltage is the trim range.

Before trimming, the typical reference is 2.405 V and the interval is [2.330, 2.510]. All chip prober values can form the normal distribution as shown in Fig. 5. The horizontal axis shows the testing reference voltage, and the vertical axis shows the ratio of the total of the chip prober. On the curve, the values around 2.405 V are valid, and others are invalid from the edge of the wafer.

All of the defective dice will be trimmed during the chip probe. In Fig. 6, the data is shown after trimming. According to the design requirement of $\pm$0.5% precision, the interval of the reference voltage is [2.483, 2.507] by the given typical value 2.495 V. The total chip-prober samples are 33560, whereas 32261 samples satisfy the request. The yield exceeds 96% and 78% of the total samples exist in the interval [2.490, 2.500] where the precision is about $\pm$0.2%. In Table 1, the reference is measured from room temperature to 125 ℃.

4. Conclusion

The 4-bit binary-weighted series-connected resistor trim scheme is used to compensate the error sources in which the base-emitter voltage spread is the main error source and the others are affected by temperature. The precision of the reference is temperature-compensated because the reference is temperature-compensated.