Fig. 1.
Block diagram of the pipeline ADC structure.
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| Citation: |
Sen Yue, Yiqiang Zhao, Ruilong Pang, Yun Sheng. A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC[J]. Journal of Semiconductors, 2014, 35(5): 055009. doi: 10.1088/1674-4926/35/5/055009
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S Yue, Y Q Zhao, R L Pang, Y Sheng. A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC[J]. J. Semicond., 2014, 35(5): 055009. doi: 10.1088/1674-4926/35/5/055009.
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A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC
DOI: 10.1088/1674-4926/35/5/055009
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Abstract
A high performance sample-and-hold (S/H) circuit used in a pipelined analog-to-digital converter (ADC) is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented. -
References
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