1. Introduction
Energetic particles induce various kinds of failures and errors while interacting with integrated circuits (ICs). The single event effect (SEE) is a serious reliability concern in the space radiation environment. Consequently, the devices to be used in space or in nuclear applications, including all CMOS devices, must be tested for their susceptibility to SEE. These tests traditionally are performed using energetic particles (protons and heavy ions) produced at accelerators. However, the pulsed laser system is known to be a valid solution to perform these tests in the laboratory, as it can provide important information on the spatial and temporal dependence of the radiation sensitivity. One of the advantages of the pulsed laser system with respect to beam testing at accelerators is that it can easily locate the position of the SEE sensitive region of ICs.
Laser SEE sensitivity mapping of ICs has been widely studied[1-7]. Most previous work studies the ICs that employ the larger feature size technology, in consideration of the laser spot size. The width of the laser pulse spot, which is constrained by the diffraction effect, cannot be less than the wavelength of the light. Take the 0.18
In this work, we demonstrate the usage of pulsed laser to study SEU sensitivity of the 0.18
2. Experiment
2.1 Experimental setup
The basic experimental set-up we have developed in the NSSC laboratory has been described in detail[8]. The device under test (DUT) is mounted on a three-dimensional moving stage, allowing 0.1
The whole system is automated to scan the laser spot over a predefined region, allowing synchronization among the DUT's motion, the emission of the laser pulses and the control of the input/output state of the device. This synchronization permits SEU sensitivity mapping of the device with an excellent reproducibility and obtains a representation of the sensitive areas.
2.2 Sensitivity test procedure
A complete scan of the test area is performed following the state diagram shown in Fig. 1. The first is initialization including the SRAM which is written with the selected data pattern, laser focus is positioned on the reference point and the energy level of the pulses is adjusted using the variable attenuator. Then the test procedure is to move the laser pulse spot from one location to the next location. At each location, a laser pulse is emitted to trigger SEU. During the procedure, the memory data of the SRAM are continually read. If any errors occur, the memory data would be recorded and refreshed. The coordinate of the location laser pulse shots would also be recorded. The experiment is finished when the predefined region is tested completely.
The test area covers four memory cells for the reliability of test results and tests the sensitivity discrepancy of adjacent memory cells. For a typical memory cell of SRAM, the SEU sensitivity characteristics vary with the logic state of the cell. The transistors of the memory cell, which are in OFF state, are sensitive to SEU. So the experiments are performed with different data patterns for the device, such as 55H, 00H.
2.3 Test device
The Hitachi HM62V8100 is an 8-Mbit static RAM organized in 1024K
3. Test results
Figure 3 shows the basic cell (dashed box outline) for the device and adjacent mirror image pairs in both the horizontal and vertical directions. The cell dimensions are 3.02
According to the different logic addresses of upsets, the locations of laser pulses inducing SEU are set to different corresponding shapes. It should be noted that the multiple bit upsets are removed when laser pulses shoot at the contiguous area between two cells for higher laser energy. The SEU sensitivity maps obtained for laser energy 3.9 nJ are shown in Fig. 4. The SEU sensitive areas are consistent with the drain areas of the blocked NMOSs of the device.
The sensitivity maps obtained for laser energy 5.0 nJ are shown in Fig. 5. The SEU sensitive regions are consistent with the drain regions of blocked NMOSs and blocked PMOSs in the micrograph of the device.
Figure 4 shows that only the drain area of blocked NMOS is responsible for SEU when the laser pulse energy is slightly above the threshold energy. In Fig. 5, the drain area of blocked NMOS and PMOS are sensitive to SEU using the higher laser pulse energy. From Figs. 4 and 5, an obvious trend is that SEU sensitive regions are symmetrical for neighboring SRAM cells with the opposite logic state. From the comparison between Fig. 4 and Fig. 5, the drain area of blocked NMOS is more sensitive than the drain area of blocked PMOS to SEU. The sensitive areas of blocked NMOS are about four times larger than the sensitive areas of blocked PMOS in Fig. 5.
The sensitivity maps obtained for laser energy 5.2 nJ with the 00H data pattern are shown in Fig. 6. The upsets for memory cell 41A93 (2) and 41AB3 (2) are "0" to "1" and the sensitive areas alter in this case. The test results of the other two memory cells are consistent with the above.
There is no need to demonstrate the SEU sensitivity mapping results for the other data patterns, which accord well with the SRAM micrograph information and the following analysis as expected.
4. TCAD simulation
To examine the SEU sensitivity of the SRAM memory cell and the validity of the laser SEU mapping results, 3-D simulations are conducted on the device model of the 0.18
As is shown in Fig. 7, 3-D TCAD simulation results are obtained with heavy ion
5. Discussions
The laser SEU mapping results presented in Figs. 4 and 5 exhibit the known sensitive areas: the drain/bulk reverse-biased junctions of blocked NMOS and PMOS transistors. As is seen in the electron micrograph of the SRAM, the drain region of pull-down transistor N1 overlaps with the drain region of read/write transistor N3 and so they are sensitive to SEU. Laser mapping results are consistent with the theoretical explanations with no need to repeat[2, 6, 10].
It can be calculated from Fig. 5 that the sensitive area of blocked NMOS is about four times larger than the sensitive area of blocked PMOS. But in the micrograph of the SRAM, the drain area of NMOS is only twice as large as the drain area of PMOS. Due to laser spot size and charge carrier diffusions near the collection volume of the drain-substrate junction[10], the obtained sensitive area by experiment is larger than the real sensitive area of the MOS transistor, especially with higher energy laser radiation[3]. Moreover, as is illustrated in Table 1, the laser SEU sensitivity mapping technique is of high precision to measure the distance between sensitive nodes of SRAM. To explain that simply, the experiment results are obtained for 00H data pattern.
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In Table 1,
It is noteworthy that SEU sensitive regions are symmetrical for neighboring SRAM cells in the horizontal direction while SEU sensitive regions are consistent for neighboring cells in the vertical direction in Fig. 5. A group of four memory cells is shown in the micrograph of the SRAM. These cells are implemented in the six-transistor format as shown in Fig. 2. It is known that the cell has two states corresponding to one diagonal pair of the central group of four transistors being in the ON state and the other diagonal pair being in the OFF state. The drain regions of transistors in the OFF state are sensitive to SEU. The sensitive area shifts from a drain to the other when the complementary data pattern is tested. From the data pattern in the experiment, the neighboring cells in the horizontal direction contain the opposite bit value and the neighboring cells in the vertical direction contain the same bit value. While in the case of Fig. 6, the sensitive regions are consistent for all the four cells, which contain the same bit value. These explain the results that the sensitivity mapping results show different images corresponding to different data patterns.
The 3-D TCAD simulation results are well consistent with the laser SEU sensitivity mapping results. The locations and shapes of sensitive areas are similar to the laser mapping results. The TCAD simulation also shows that laser mapping is reliable for this deep submicron technology device.
Moreover, by the test we have obtained the distance between sensitive nodes in neighboring cells, which is useful for modeling SEE and radiation hardened by design (RHBD) optimization. A single ion may induce upsets in more than one adjacent cell in highly scaled memory. The multiple-bit upsets (MBUs) is a major contributor to the SER rate and the information on sensitive area spatial separation is essential for error-rate prediction codes. In addition, the experiment results show that the size of sensitive areas increases with increasing laser energy. So it is possible to construct the upset cross section versus laser energy using sensitivity maps.
6. Conclusion
This work has demonstrated the technique of pulsed laser SEU sensitivity mapping of 0.18