J. Semicond. > 2014, Volume 35 > Issue 7 > 075003
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SEMICONDUCTOR INTEGRATED CIRCUITS

A ΔΣ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

Mingyi Chen, Xiaoji Chu, Peng Yu, Jun Yan and Yin Shi

+ Author Affiliations

 Corresponding author: Chen Mingyi, Email:tjucmy@126.com

DOI: 10.1088/1674-4926/35/7/075003

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Abstract: A Δ Σ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise (from 10 to 100 kHz) below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz (at 1 MHz offset) are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.

Key words: FM tuner, frequency synthesizer, low noise filter, Δ Σ modulator, quantization noise suppression



[1]
Ruffieux D, Melly T, Peiris V, et al. A 1.2-mW RDS receiver for portable applications. IEEE J Solid-State Circuits, 2004, 39(7): 995 doi: 10.1109/JSSC.2004.829971
[2]
Jones C G, Beghein C C. Low noise filter. US Patent, No.6891412 B1, 2005
[3]
Chen Mingyi, Chu Xiaojie, Yu Peng, et al. A 55 nm CMOS Δ Σ fractional-N frequency synthesizer for WLAN transceivers with low noise filter. Journal of Semiconductors, 2013, 34(10): 105001 doi: 10.1088/1674-4926/34/10/105001
[4]
Jin J, Liu X, Mo T, et al. Quantization noise suppression in fractional-N PLLs utilizing glitch-free phase switching multi-modulus frequency divider. IEEE Trans Circuits Syst, 2012, 59(5): 926 doi: 10.1109/TCSI.2012.2189042
[5]
Yang Y C, Yu S A, Wang T, et al. A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell. IEEE Microw Wireless Compon Lett, 2005, 15(11): 754 doi: 10.1109/LMWC.2005.858978
[6]
Yang Y C, Yu S A, Liu Y H, et al. A quantization noise suppression technique for Δ Σ fractional-N frequency synthesizers. IEEE J Solid -State Circuits, 2006, 41(11): 2500 doi: 10.1109/JSSC.2006.883325
[7]
Lou Liheng, Sun Lingling, Gao Haijun, et al. A wideband frequency synthesizer with VCO and AFC co-design for fast calibration. Journal of Semiconductors, 2013, 34(1): 015008 doi: 10.1088/1674-4926/34/1/015008
[8]
Shin J, Shin H. A 1.9-3.8 GHz delta-sigma fractional-N PLL frequency synthesizer with fast auto-calibration of loop bandwidth and VCO frequency. IEEE J Solid-State Circuits, 2012, 47(3): 665 doi: 10.1109/JSSC.2011.2179733
Fig. 1.  Block diagram of the proposed ΔΣ fractional-N frequency synthesizer.

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Fig. 2.  (a) Traditional low pass loop filter. (b) Proposed low noise filter.

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Fig. 3.  (a) Magnitude and phase frequency response of the traditional low pass loop filter and low noise filter. (b) Output noise voltage of the traditional low pass loop filter and low noise filter.

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Fig. 4.  (a) Block diagram of divider-by 2/2.5 prescalor. (b) Schematic of 1/1.5 divider cell.

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Fig. 5.  Timing chart of the 1/1.5 divider cell in divide-by-1.5 mode.

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Fig. 6.  Schematic of the VCO and VCO buffer.

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Fig. 7.  Measured tuning curve of the VCO.

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Fig. 8.  Block diagram of the ΔΣ modulator.

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Fig. 9.  Die photograph of the synthesizer.

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Fig. 10.  (a) Phase noise performance of 76 MHz with QN suppression. (b) Phase noise performance of 76 MHz without QN suppression.

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Fig. 11.  Frequency spectrum of 79 MHz.

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Fig. 12.  Transient response of locking process.

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Fig. 13.  RMS phase error integrated from 100 Hz to 10 MHz.

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Table 1.   Performance comparison with other related works.
[1]
Ruffieux D, Melly T, Peiris V, et al. A 1.2-mW RDS receiver for portable applications. IEEE J Solid-State Circuits, 2004, 39(7): 995 doi: 10.1109/JSSC.2004.829971
[2]
Jones C G, Beghein C C. Low noise filter. US Patent, No.6891412 B1, 2005
[3]
Chen Mingyi, Chu Xiaojie, Yu Peng, et al. A 55 nm CMOS Δ Σ fractional-N frequency synthesizer for WLAN transceivers with low noise filter. Journal of Semiconductors, 2013, 34(10): 105001 doi: 10.1088/1674-4926/34/10/105001
[4]
Jin J, Liu X, Mo T, et al. Quantization noise suppression in fractional-N PLLs utilizing glitch-free phase switching multi-modulus frequency divider. IEEE Trans Circuits Syst, 2012, 59(5): 926 doi: 10.1109/TCSI.2012.2189042
[5]
Yang Y C, Yu S A, Wang T, et al. A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell. IEEE Microw Wireless Compon Lett, 2005, 15(11): 754 doi: 10.1109/LMWC.2005.858978
[6]
Yang Y C, Yu S A, Liu Y H, et al. A quantization noise suppression technique for Δ Σ fractional-N frequency synthesizers. IEEE J Solid -State Circuits, 2006, 41(11): 2500 doi: 10.1109/JSSC.2006.883325
[7]
Lou Liheng, Sun Lingling, Gao Haijun, et al. A wideband frequency synthesizer with VCO and AFC co-design for fast calibration. Journal of Semiconductors, 2013, 34(1): 015008 doi: 10.1088/1674-4926/34/1/015008
[8]
Shin J, Shin H. A 1.9-3.8 GHz delta-sigma fractional-N PLL frequency synthesizer with fast auto-calibration of loop bandwidth and VCO frequency. IEEE J Solid-State Circuits, 2012, 47(3): 665 doi: 10.1109/JSSC.2011.2179733

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    Received: 13 January 2014 Revised: 12 February 2014 Online: Published: 01 July 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(7): 075003
      Mingyi Chen, Xiaoji Chu, Peng Yu, Jun Yan, Yin Shi. A ΔΣ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique[J]. Journal of Semiconductors, 2014, 35(7): 075003. doi: 10.1088/1674-4926/35/7/075003 ****M Y Chen, X J Chu, P Yu, J Yan, Y Shi. A ΔΣ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique[J]. J. Semicond., 2014, 35(7): 075003. doi: 10.1088/1674-4926/35/7/075003.
      Citation:
      Mingyi Chen, Xiaoji Chu, Peng Yu, Jun Yan, Yin Shi. A ΔΣ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique[J]. Journal of Semiconductors, 2014, 35(7): 075003. doi: 10.1088/1674-4926/35/7/075003 ****
      M Y Chen, X J Chu, P Yu, J Yan, Y Shi. A ΔΣ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique[J]. J. Semicond., 2014, 35(7): 075003. doi: 10.1088/1674-4926/35/7/075003.
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      A ΔΣ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

      DOI: 10.1088/1674-4926/35/7/075003

      • Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

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      • Corresponding author: Chen Mingyi, Email:tjucmy@126.com
      • Received Date: 2014-01-13
      • Revised Date: 2014-02-12
      • Published Date: 2014-07-01

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