Fig. 1.
Common-source flash array using split-gate flash memory cell.
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| Citation: |
Shengbo Zhang, Guangjun Yang, Jian Hu, Jun Xiao. A novel sourceline voltage compensation circuit for embedded NOR flash memory[J]. Journal of Semiconductors, 2014, 35(7): 075007. doi: 10.1088/1674-4926/35/7/075007
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S B Zhang, G J Yang, J Hu, J Xiao. A novel sourceline voltage compensation circuit for embedded NOR flash memory[J]. J. Semicond., 2014, 35(7): 075007. doi: 10.1088/1674-4926/35/7/075007.
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A novel sourceline voltage compensation circuit for embedded NOR flash memory
DOI: 10.1088/1674-4926/35/7/075007
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Abstract
A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data "0". So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data "0" are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8×64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process. -
References
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